Bridge device with page-access based processor interface

• US 20090055569A1
• Filed: 08/14/2008
• Published: 02/26/2009
• Est. Priority Date: 08/24/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Rajamanickam, Jagadeesan, Maheshwari, Dinesh
• Granted Patent: US 8,037,228 B2
• Time in Patent Office: Days
• US Class Current: 710/311
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

An integrated circuit bridge device can include a first interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus. A second interface circuit can be coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit. In addition, a controller circuit formed in the same substrate as the first and second interface circuits can be configured to enable data transfers between the third interface circuit and the first interface circuits via the buffer circuit.

Claims

1. An integrated circuit bridge device, comprising:

a first interface circuit coupled to a buffer circuit and configurable in response to configuration information to receive command information, address information, and data values on a same multi-bit input/output (I/O) bus;

a second interface circuit coupled to the buffer circuit and configured to communicate according to a first communication protocol different from that executable by the first interface circuit; and

a controller circuit formed in the same substrate as the first and second interface circuits, the controller circuit configured to enable data transfers between the first interface circuit and the second interface circuits via the buffer circuit.

2. The bridge device of claim 1, wherein:

the first interface circuit includes a port register that stores values generated in response to at least the command information and address information, the port register circuit being accessible by the controller circuit.

3. The bridge device of claim 2, wherein:

the first interface circuit is configurable to generate values for the port register circuit differently based on port configuration values, the port configuration values signifying variations in command information and address information input.

4. The bridge device of claim 3, wherein:

the port configuration values differentiate between command information and address information input formats, including

command-address sequences that start with a command value and follow with at least one address value,

command-address sequences that start with a first command value, follow with at least one address value, and

conclude with a second command value, and the number of address values received in a sequence.

5. The bridge device of claim 2, wherein:

the first interface circuit further includes second interface logic circuitry that generates a notification signal in response to predetermined control input signals being received by the first interface circuit; and

the controller circuit comprises a processor and an instruction memory and is configured to read data from the port register circuit in response to the notification signal and execute predetermined operations according to at least one value read from the port register circuit.

6. The bridge device of claim 1, further including:

the first interface circuit includes a busy signal path coupled between the controller circuit and a busy signal output pin, the busy signal providing an indication of the status of a device connected to at least the second interface circuit.

7. The bridge device of claim 1, further including:

an I/O data path coupled between the I/O bus and the buffer circuit;

the first interface circuit further includes an enable signal path that couples at least one enable signal received at the first I/F to a data timing input of the buffer circuit; and

the buffer circuit controls data transfers on the I/O bus in response to at least one signal received at the data timing input.

8. The bridge device of claim 1, further including:

an I/O data path coupled between the I/O bus and the buffer circuit that includes at least two separate multi-bit internal buses; and

the buffer circuit is configurable to output data onto and input data from only one of the multi-bit internal buses in a first buffer configuration, and output data onto and input data from both multi-bit internal buses in parallel in a second buffer configuration.

9. The bridge device of claim 1, wherein:

the buffer circuit comprises

a plurality of dual port memory sections, each having a first port coupled to the first interface circuit and a second port, and

a multiplexer-demultiplexer circuit (MUX/de-MUX) having MUX output and de-MUX input coupled to the first ports of the dual port memory sections, a first MUX input and first de-MUX output coupled to the first interface circuit, and a second MUX input and second de-MUX output coupled to a third interface circuit configurable to interface with an external device separate from any devices connected to the first and second interfaces.

10. The bridge device of claim 1, further including:

the controller circuit is configured to enable transfers of data between the first interface circuit and the second interface circuit in response to predetermined first address information, and enable transfers of data between the first interface circuit and a third interface circuit in response to predetermined second address information.

11. A bridge device, comprising:

a page-access (PA) processor interface having a plurality of processor input/outputs (I/Os) for receiving processor commands, addresses and data on a same set of I/Os;

a buffer circuit having a plurality of storage locations logically dividable into a plurality of endpoints; and

a controller circuit comprising a processor and an instruction memory configurable to assign endpoints of the buffer circuit to at least a host interface having host inputs/outputs (I/Os) configured to receive data in a predetermined packet format, or to a storage interface having storage I/Os configurable to access data from a storage device, and to enable a data transfer path between the processor interface and a predetermined endpoint based on at least address information received on the processor I/Os.

12. The bridge device of claim 11, wherein:

the host interface comprises a universal serial bus interface having at least a first data I/O line and a second data I/O line.

13. The bridge device of claim 11, wherein:

the processing section is further configurable to, in response to at least a first predetermined command and address value at the PA processor interface, enable a data transfer path from the PA processor interface to a predetermined endpoint, and enable a data transfer path between the host interface and the predetermined endpoint.

14. The bridge device of claim 11, wherein:

the processing section is further configurable to, in response to at least a first predetermined command and address value at the PA processor interface, enable a data transfer path from the PA processor interface to a predetermined endpoint, and enable a data transfer path between the storage interface and the predetermined endpoint.

15. A method of enabling a page-access based processor to access non-page-access based devices, comprising the steps of:

(a) associating buffer locations with one of at least a second interface and a third interface of the same integrated circuit device; and

(b) in response to a predetermined sequence of command data and address data received on a same set of input/output (I/O) lines at a first interface of the integrated device, coupling the I/O lines to one of the buffer locations.

16. The method of claim 15, further including:

step (b) includes selecting between one buffer location associated with the second interface and one buffer location associated with the third interface based on at least a portion of the address data.

17. The method of claim 15, further including:

(c) connecting a non-page access device different than the integrated circuit device to the second interface; and

(d), after step (b), transferring request data from one of the buffer locations to the non-page access device, and executing a predetermined function of the non-page access device in response to the request data.

18. The method of claim 15, further including:

(c) in response to the predetermined sequence of command data and address data, generating a busy indication at the first interface that indicates the status of an operation executed on a non-page access device attached to the second interface.

19. The method of claim 15, wherein:

step (a) includes mapping buffer locations to logical endpoints to allow a controller circuit formed on the integrated circuit to control access to the buffer locations based on an endpoint value; and

step (b) includes identifying a destination endpoint based on at least the address data.

20. The method of claim 15, further including:

(c) prior to step (a), coupling a non-NAND flash device to at least the third interface; and

step (b) includes

the command data and address data being in a predetermined format for a NAND flash device,

executing a sequence of predetermined processor instructions in response to the command and address data to generate configuration values, and

in response to the configuration values, coupling the I/O lines to one of the buffer locations and coupling the one of the buffer locations to the third interface to transfer data between the first interface and third interface in response to the command data and address data.