Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design

• US 20090055668A1
• Filed: 08/21/2007
• Published: 02/26/2009
• Est. Priority Date: 08/21/2007
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Srouji, Johny, Fernsler, Matthew Earl, Swanson, Todd, Jacobson, Hans Mikael
• Granted Patent: US 8,073,669 B2
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Claims

1. A method of power conservation in a pipeline electronic device, comprising:

providing the pipeline electronic device with a plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage;

simulating operation of the pipeline electronic device to determine simulation results that specify selected logic elements that may be clock-gated under predetermined conditions; and

clock-gating the selected logic elements of the pipeline electronic device based on the simulation results to achieve power conservation.

2. The method of claim 1, wherein the simulating step includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.

3. The method of claim 1, wherein the simulating step includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that are already clock-gated from clock cycle to clock cycle.

4. The method of claim 1, wherein the simulating step includes analyzing the first pipeline stage for clock-gating opportunities by monitoring the second pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.

5. The method of claim 1, wherein the simulating step includes analyzing the first pipeline stage for clock-gating opportunities by monitoring the second pipeline stage for second pipeline logic elements that are already clock-gated from clock cycle to clock cycle.

6. The method of claim 1, wherein the simulating step further comprises generating, by a simulator, a simulation model from a net list that describes the pipeline electronic device.

7. The method of claim 6, further comprising monitoring, by the simulator, the logic elements of the first and second pipeline stages from clock cycle to clock cycle to locate clock-gating opportunities.

8. The method of claim 1, wherein the simulator identifies clock gating opportunities thus providing identified clock gating opportunities, the method further comprising weighting one identified clock-gating opportunity with respect to another clock-gating opportunity to determine which clock-gating opportunity provides more power saving.

9. A method of designing a pipeline electronic device comprising:

designing an first pipeline electronic device including a plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage;

simulating operation of the first pipeline electronic device to determine simulation results that specify selected logic elements that may be clock-gated under predetermined conditions; and

modifying the first pipeline electronic device to form a second pipeline electronic device that clock-gates the selected logic elements based on the simulation results to achieve power conservation.

10. The method of claim 9, wherein the simulating step includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.

11. The method of claim 9, wherein the simulating step includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that are already clock-gated from clock cycle to clock cycle.

12. The method of claim 9, wherein the simulating step includes analyzing the first pipeline stage for clock-gating opportunities by monitoring the second pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.

13. The method of claim 9, wherein the simulating step includes analyzing the first pipeline stage for clock-gating opportunities by monitoring the second pipeline stage for second pipeline logic elements that are already clock-gated from clock cycle to clock cycle.

14. The method of claim 9, wherein the simulating step further comprises generating, by a simulator, a simulation model from a net list that describes the pipeline electronic device.

15. The method of claim 14, further comprising monitoring, by the simulator, the logic elements of the first and second pipeline stages from clock cycle to clock cycle to locate clock-gating opportunities.

16. The method of claim 9, wherein the simulator identifies clock gating opportunities thus providing identified clock gating opportunities, the method further comprising weighting one identified clock-gating opportunity with respect to another clock-gating opportunity to determine which clock-gating opportunity provides more power saving.

17. An information handling system (IHS), comprising:

a memory,

a pipeline electronic processor device, coupled to the memory, the pipeline electronic processor device including;

a plurality of pipeline stages including first and second pipeline stages that each include logic elements that may be clock-gated, each pipeline stage supplying information to a downstream pipeline stage, wherein selected logic elements are clock-gated based on a simulation of the pipeline electronic processor device that specifies the selected logic elements that may be clock-gated under predetermined conditions to achieve power conservation.

18. The IHS of claim 17, wherein the simulation includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.

19. The IHS of claim 17, wherein the simulation includes analyzing the second pipeline stage for clock-gating opportunities by monitoring the first pipeline stage for first pipeline logic elements that are already clock-gated from clock cycle to clock cycle.

20. The IHS of claim 17, wherein the simulation includes analyzing the first pipeline stage for clock-gating opportunities by monitoring the second pipeline stage for first pipeline logic elements that do not change logic state from clock cycle to clock cycle.