Asynchronous first in first out interface and operation method thereof

• US 20090055677A1
• Filed: 08/21/2007
• Published: 02/26/2009
• Est. Priority Date: 08/21/2007
• Status: Active Grant

• Current Assignee: RichWave Technology Corp
• Original Assignee: RichWave Technology Corp
• Inventors: Chen, Tse-Peng
• Granted Patent: US 7,996,704 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

The invention provides an asynchronous first in first out (FIFO) interface and operation method wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous. The asynchronous FIFO interface comprises a FIFO buffer, a clock controller and a variable integer divider. The FIFO buffer inputs at least one data with the write-in clock, and outputs the at least one data with the read-out clock. The clock controller outputs a clock control signal according to a number of data stored in the FIFO buffer. The variable integer divider divides a first signal to generate the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

Claims

1. An asynchronous first in first out (FIFO) interface, wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous, comprising:

a FIFO buffer, inputting digital data with the write-in clock, outputting the digital data with the read-out clock;

a clock controller, outputting a clock control signal according to a number of data stored in the FIFO buffer; and

a variable integer divider, for dividing a first signal to generate one of the read-out clock or the write-in clock by an integer divisor controlled by the clock control signal in order to adjust the number of data stored in the FIFO buffer.

2. The asynchronous FIFO interface as claimed in claim 1, wherein when the number of data stored in the FIFO buffer comes to a first threshold or a second threshold lower than the first threshold, the integer divisor is changed in order to adjust the number of data stored in the FIFO buffer.

4. The asynchronous FIFO interface as claimed in claim 1, wherein

when the asynchronous FIFO interface receives the digital data from an analog-to-digital converter (ADC), a clock of the ADC is the write-in clock;

when the asynchronous FIFO interface outputs the digital data to an digital-to-analog converter (DAC), a clock of the DAC is the read-out clock.

5. The asynchronous FIFO interface as claimed in claim 1, wherein the first signal is generated by a low jitter source.

6. The asynchronous FIFO interface as claimed in claim 5, wherein the asynchronous FIFO interface, the ADC, the DAC and the low jitter source are within a single integrated circuit.

7. The asynchronous FIFO interface as claimed in claim 1, wherein the read-out clock and the write-in clock use a single reference source.

8. The asynchronous FIFO interface as claimed in claim 1, wherein the integer divisor is changed between two consecutive integers.

3. (canceled)

9. An operation method of an asynchronous first in first out (FIFO) interface, wherein a read-out clock and a write-in clock of the asynchronous FIFO interface is asynchronous, comprising:

inputting digital data to a FIFO buffer with the write-in clock;

detecting a number of data stored in the FIFO buffer;

dividing a first signal to generate one of the read-out clock or the write-in clock by an integer divisor to adjust the number of data stored in the FIFO buffer wherein the integer divisor is controlled according to the number of data stored in the FIFO buffer; and

outputting the digital signal from the FIFO buffer with the read-out clock.

10. The operation method of the asynchronous FIFO interface as claimed in claim 9, wherein changing the integer divisor when the number of data stored in the FIFO buffer comes to a first threshold or a second threshold lower than the first threshold in order to adjust the number of data stored in the FIFO buffer.

11-14. -14. (canceled)

15. A circuit with an asynchronous first in first out (FIFO) interface, comprising:

a first circuit portion with a first signal generated by a first source;

a second circuit portion, operating according to a second signal and communicating at least one data with the first circuit portion;

an asynchronous FIFO interface, comprising;

a FIFO buffer device, coupled between a the first and second circuit portions to buffer the at least one data communicated between the first and second circuit portions;

wherein the FIFO buffer device inputs the at least one data according to a write-in clock and outputs the at least one data according to a read-out clock;

a clock controller device, outputting a least one clock control signal according to a number of data stored in the FIFO buffer device; and

a variable integer divider device, dividing the first signal to generate the write-in clock for the FIFO buffer device when the at least one data transmitted from the first circuit portion to the second circuit portion, and to generate the read-out clock for the FIFO buffer device when the at least one data transmitted from the second circuit portion to the first circuit portion, wherein the write-in clock or the read-out lock generated by dividing the first signal is asynchronous wit the second signal.

16. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the FIFO buffer device outputs data stored in the FIFO buffer device according to the second signal when the at least one data transmitted from the first circuit portion to the second circuit portion, and inputs data to be stored in the FIFO buffer device according to the second signal when the at least one data transmitted from the second circuit portion to the first circuit portion.

17. The circuit with the asynchronous FIFO interface as claimed in claim 16, wherein:

the first circuit portion further comprising;

a radio frequency (RF) front end receiver, receiving a RF signal, down-converting the RF signal to at least one analog signal according o at least one local signal;

a analog-to-digital converter (ADC), converting the at least one analog signal to the at least one data with the write-in clock;

wherein the at least one data is inputted into the FIFO buffer device according to the write-in clock and is outputted from the FIFO buffer device according to the second signal.

18. The circuit with the asynchronous FIFO interface as claimed in claim 16, wherein:

the first circuit portion further comprising;

a radio frequency (RF) front end transmitter, up-converting at least one analog signal to the RF signal according to at least one local signal, transmitting the RF signal;

a digital-to-analog converter (DAC), converting the at least one data to the at least one analog signal with the read-in clock;

wherein the at least one data is inputted into FIFO buffer device according to the second signal and is outputted from FIFO buffer device according to the read-out clock.

19. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein when the number of data stored in the first FIFO buffer comes to a first threshold or a second threshold lower than the first threshold, the first integer divisor is changed in order to adjust the number of data stored in the first FIFO.

21. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein:

the first circuit portion further comprising;

a radio frequency (RF) front end receiver, receiving a first RF signal, down-converting the first RF signal to at least one first analog signal according to at least one local signal;

a radio frequency (RF) front end transmitter, up-converting at least one second analog signal to the second RF signal according to the at least one local signal, transmitting the second RF signal;

a analog-to-digital converter (ADC), converting the at least one first analog signal to at least one first data with a first write-in clock;

a digital-to-analog converter (DAC), converting the at least one second analog signal to at least one second data with a second read-out clock;

wherein the at least one data comprises the at least one first and the second data; and

the FIFO buffer device further comprising;

a first FIFO buffer, coupled between the first and second circuit portions, inputting the at least one first data according to the first write-in clock, outputting the at least one first data according to a second clock; and

a second FIFO buffer, coupled between the first and second circuit portions, inputting the at least one second data according to the second clock, outputting the at least one second data according to a second read-out clock;

the clock controller device further comprising;

a first clock controller, outputting a first write-in clock control signal according to a number of data stored in the first FIFO buffer; and

a second clock controller, outputting a second read-out control signal according to a number of data stored in the second FIFO buffer;

the variable integer divider device further comprising;

a first variable integer divider, dividing the first signal to generate the first write-in clock by a first integer divisor controlled by the first write-in clock control signal in order to adjust the number of data stored in the first FIFO buffer; and

a second variable integer divider, dividing the first signal to generate the second read-out clock by a second integer divisor controlled by the second read-out clock control signal in order to adjust the number of data stored in the second FIFO buffer.

22. The circuit with the asynchronous FIFO interface as claimed in claim 21, wherein

when the number of data stored in the first FIFO buffer comes to a first threshold or a second threshold lower than the first threshold, the first integer divisor is changed in order to adjust the number of data stored in the first FIFO;

when the number of data stored in the second FIFO buffer comes to a third threshold or a fourth threshold lower than the third threshold, the second integer divisor is changed in order to adjust the number of data stored in the second FIFO.

24. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the first circuit portion, the second circuit portion and the asynchronous FIFO interface are within a single chip.

25. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the first source further comprising:

a voltage control oscillator (VCO), outputting a VCO signal according to a control voltage;

a synthesizer, coupled to the VCO, outputting the control voltage according to a single reference source and the VCO signal; and

a local generator, coupled to the VCO, outputting at least one local signal according to the VCO signal;

wherein the first signal can be provided by the VCO or the local generator.

26. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the second signal is a high jitter signal.

27. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the second signal is a fixed frequency signal.

28. The circuit with the asynchronous, FIFO interface as claimed in claim 26, wherein the second signal is generated by a ring oscillator.

29. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the first signal is a low jitter signal.

30. The circuit with the asynchronous FIFO interface as claimed in claim 15, wherein the first signal is a variable frequency signal.

20. (canceled)

23. (canceled)

31. An operation method of a transceiver with an asynchronous interface, comprising:

receiving at least one first radio frequency (RF) signal,

down-converting the at least one first RF signal to at least one first analog signal;

detecting a number of data stored in a first first in first out(FIFO) buffer;

dividing a first signal to generate a first clock by a first integer divisor to adjust the number of data stored in the first FIFO buffer wherein the first integer divisor is controlled according to the number of data stored in the first FIFO buffer;

converting the at least one first analog signal to at least one first data with the first clock;

inputting the at least one first data to the first FIFO buffer with the first clock;

outputting the at least one first data with a second signal from the first FIFO buffer, wherein the first clock and the second signal are asynchronous;

inputting at least one second data to a second FIFO buffer with the second signal;

detecting a number of data stored in the second FIFO buffer;

dividing the first signal to generate the second clock by a second integer divisor to adjust the number of data stored in the second FIFO buffer wherein the second integer divisor is controlled according to the number of data stored in the second FIFO buffer;

outputting the at least one second data from the second FIFO buffer with the second clock, wherein the second clock and the digital clock is asynchronous;

converting the at least one second data to at least one second analog signal with the second clock;

up-converting the at least one second analog signal to at least one second RF signal; and

transmitting the at least one second RF signal.

32. An operation method of a transceiver with an asynchronous interface as claimed in claim 31, wherein:

when the number of data stored in the first FIFO buffer comes to a first threshold or a second threshold lower than the first threshold, the first integer divisor is changed in order to adjust the number of data stored in the first FIFO buffer; and

when the number of data stored in the second FIFO buffer comes to a third threshold or a fourth threshold lower than the third threshold, the second integer divisor is changed in order to adjust the number of data stored in the second FIFO buffer.

33. (canceled)