Clock processors in high-speed signal converter systems
First Claim
1. A clock processor for processing an input clock of a system, comprising:
- a duty cycle stabilizer configured to respond to said input clock to initiate a first system portion of each system cycle of a system clock and to include a control loop to provide an error signal that controls a second system portion of said system cycle to thereby maintain a selected duty cycle of said system clock; and
a data clock aligner configured to respond to said error signal and provide a data clock that is delayed by a selected delay from said system clock.
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Accused Products
Abstract
Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.
27 Citations
20 Claims
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1. A clock processor for processing an input clock of a system, comprising:
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a duty cycle stabilizer configured to respond to said input clock to initiate a first system portion of each system cycle of a system clock and to include a control loop to provide an error signal that controls a second system portion of said system cycle to thereby maintain a selected duty cycle of said system clock; and a data clock aligner configured to respond to said error signal and provide a data clock that is delayed by a selected delay from said system clock. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 20)
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15. A clock processor for processing an input clock of a system, comprising:
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a control loop that includes a delay network and is configured to apply an error signal to said delay network for generation of an output clock in response to said input clock; and a data clock aligner that includes first and second aligner delay generators arranged to respectively initiate first and second data portions of each data cycle of a data clock that is delayed by a selected delay from said system clock wherein said first and second aligner delay generators are each configured to have an aligner sensitivity to said error signal such that said first and second data portions are initiated after a selected aligner time delay.
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18. A signal converter system for converting an analog input signal into a corresponding digital code in response to an input clock, the system comprising:
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a pipelined arrangement of converter stages that successively process said input signals to corresponding digital bits in response to a system clock derived from said input clock; an alignment/correction logic configured to process said digital bits into said digital code; a duty cycle stabilizer configured to respond to said input clock to initiate a first system portion of each system cycle of said system clock and to include a control loop to provide an error signal that controls a second system portion of said system cycle to thereby maintain a selected duty cycle of said system clock; and a data clock aligner configured to respond to said error signal and provide a data clock that is delayed by a selected delay from said system clock wherein said data clock provides a temporal reference for said digital code. - View Dependent Claims (19)
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Specification