METHOD AND APPARATUS FOR EMBEDDED MEMORY SECURITY

• US 20090055906A1
• Filed: 08/20/2007
• Published: 02/26/2009
• Est. Priority Date: 08/20/2007
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: von Wendorff, Wilhard
• Application Number:
  US11/841,171
• Publication Number:
  US 20090055906A1
• Time in Patent Office: Days
• US Class Current: 726/5
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

A method and apparatus for protecting data in a memory block from unauthorized access. When writing or reading data to or from the memory block an error correction code (ECC) is used to calculate an ECC value, wherein the calculation of the ECC value is based on a combination of the data and a password provided to the memory block prior to reading or writing. In case the calculated ECC value does not match a stored ECC value a write or read error is signalled to the device requesting the operation.

Claims

1. A method for protecting data in a memory block of a digital processing system, comprising:

providing a password to the memory block prior to a write data or read data request;

calculating an error correction code (ECC) value based on a combination of the data and the password, and

comparing the calculated ECC value to an ECC value stored in the memory block.

2. The method of claim 1, wherein the password is split up in at least two portions, the portions being merged to one password in the memory block.

3. The method of claim 2, wherein one portion of the password identifies the device in the digital processing system requesting the write or read data request.

4. The method of claim 1, wherein the device requesting the write or read data request provides the password to the memory block.

5. The method of claim 4, wherein the requesting device writes the password to the memory block bypassing a regular address decoding logic.

6. The method of claim 1, wherein the combination of the data and the password is one of a concatenation or a binary OR or a binary AND or a binary XOR operation or a combination of these operations.

7. The method of claim 1, wherein the ECC logic modifies the data in case of mismatch between a calculated and a stored ECC value.

8. The method of claim 7, wherein a mismatch between a calculated ECC value and a stored ECC value causes the ECC logic to modify the password and wherein the modified password is used as valid password in at least one subsequent read data operation.

9. The method of claim 8, wherein the password is modified in each read data operation.

10. The method of claim 1, wherein the digital processing system is included in an engine management system.

11. A digital processing system comprising:

at least one device requesting write data or read data requests via a communication link from a memory block,

wherein the memory block includes a storage unit for storing a password; and

an error correction code (ECC) logic, wherein the ECC logic is adapted to calculate an ECC value based on a combination of the data and the password.

12. The system of claim 11, wherein the ECC logic is adapted to directly read and write the password to the storage unit bypassing an address logic.

13. The system of claim 11, wherein the device requesting the read or write operation includes a device for storing the password.

14. The system of claim 13, wherein the device for storing the password is a core register in a central processing unit included in the system.

15. The system of claim 11, wherein the device requesting the read or write operation is adapted to provide an identifier identifying the device as a first portion of the password to the memory block and at least a second portion of the password.

16. The system of claim 15, wherein the memory block is adapted to merge the at least two password portions into one password.

17. The system of claim 16, wherein the merge operation is one of a concatenation or a binary AND or a binary OR or a binary XOR operation.

18. The system of claim 11, wherein the ECC logic is adapted for modifying the password in case of a mismatch between a calculated ECC value and a stored ECC value.

19. A digital processing system comprising:

at least one device requesting write data or read data requests via a communication link from a memory block;

wherein the memory block includes a storage unit for storing a password; and

means for calculating an error correction code (ECC) value based on a combination of the data and the password.