Solar cell and fabricating process thereof

• US 20090056807A1
• Filed: 01/02/2008
• Published: 03/05/2009
• Est. Priority Date: 08/28/2007
• Status: Abandoned Application

• Current Assignee: Mosel Vitelic Incorporated
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Chen, Hsi-Chieh, Chu, Chih-Hsun
• Application Number:
  US12/003,806
• Publication Number:
  US 20090056807A1
• Time in Patent Office: Days
• US Class Current: 136/261
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1864 Annealing
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A solar cell includes a semiconductor substrate, an emitter layer, at least one emitter contact region and at least one first electrode. The emitter layer is formed on at least one surface of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The emitter contact region is formed on portions of the emitter layer and has the same type of dopant as the emitter layer. The emitter contact region has a higher dopant concentration than the emitter layer. The first electrode is coupled with the emitter contact region.

Claims

1. A solar cell comprising:

a semiconductor substrate;

an emitter layer formed on at least one surface of said semiconductor substrate, wherein a p-n junction is formed between said emitter layer and said semiconductor substrate;

at least one emitter contact region formed on portions of said emitter layer and has the same type of dopant as said emitter layer, wherein said emitter contact region has a higher dopant concentration than said emitter layer; and

at least one first electrode coupled with said emitter contact region.

2. The solar cell according to claim 1 further including at least one second electrode, which is coupled with said semiconductor substrate.

3. The solar cell according to claim 2 further including a back surface field layer, which is formed and interconnected between said semiconductor substrate and said second electrode.

4. The solar cell according to claim 1 further including an anti-reflective coating, which is formed between said first electrode and said emitter layer.

5. The solar cell according to claim 1 wherein said first electrode is made of silver and said second electrode is made of aluminum.

6. The solar cell according to claim 1 wherein said first semiconductor substrate is a first type of semiconductor substrate and said emitter layer is a second type of semiconductor diffusion layer.

7. The solar cell according to claim 6 wherein said first semiconductor substrate is a p-type silicon substrate and said emitter layer is an n-type diffusion layer.

8. The solar cell according to claim 1 wherein said emitter contact region is substantially parallel with said first electrode, and the width of said emitter contact region is substantially greater than that of said first electrode.

9. The solar cell according to claim 1 wherein said emitter contact region is implanted with the same type of dopant as said emitter layer and partially extended to said semiconductor substrate.

10. The solar cell according to claim 1 wherein said surface of said semiconductor substrate has a textured structure having concave and convex patterns formed thereon.

11. A process of fabricating a solar cell, comprising steps of:

(a) providing a semiconductor substrate;

(b) forming an emitter layer on at least one surface of said semiconductor substrate and forming a p-n junction between said emitter layer and said semiconductor substrate;

(c) forming at least one emitter contact region on portions of said emitter layer, wherein said emitter contact region has the same type of dopant as said emitter layer and said emitter contact region has a higher dopant concentration than said emitter layer; and

(d) forming at least one first electrode above said emitter layer and coupled with said emitter contact region.

12. The process according to claim 11 wherein said step (a) further includes a step of forming a textured structure having concave and convex patterns on said surface of said semiconductor substrate.

13. The process according to claim 11 wherein said step (c) includes sub-steps of:

(c1) forming at least one emitter contact region on portions of said emitter layer;

(c2) removing a phosphosilicate glass layer, which is formed on said emitter layer; and

(c2) forming an anti-reflective coating on said emitter layer.

14. The process according to claim 13 wherein said step (c1) is implemented by a laser-writing annealing procedure.

15. The process according to claim 13 wherein said step (d) includes sub-steps of:

(d1) forming a first conductor layer on a back-lighted side of said semiconductor substrate and a second conductor layer on said anti-reflective coating; and

(d2) firing said second conductor layer into said first electrode, forming a back surface field layer on said back-lighted side, and changing a portion of said first conductor layer into a second electrode.

16. The process according to claim 15 wherein said first electrode is made of silver and said second electrode is made of aluminum.

17. The process according to claim 11 wherein said first semiconductor substrate is a first type of semiconductor substrate and said emitter layer is a second type of semiconductor diffusion layer.

18. The process according to claim 17 wherein said first semiconductor substrate is a p-type silicon substrate and said emitter layer is an n-type diffusion layer.

19. The process according to claim 11 wherein said emitter contact region is substantially parallel with said first electrode, and the width of said emitter contact region is substantially greater than that of said first electrode.

20. The process according to claim 11 wherein said emitter contact region is implanted with the same type of dopant as said emitter layer and partially extended to said semiconductor substrate.