Multiple chips bonded to packaging structure with low noise and multiple selectable functions

• US 20090056988A1
• Filed: 11/12/2008
• Published: 03/05/2009
• Est. Priority Date: 05/19/2000
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Application Number:
  US12/269,054
• Publication Number:
  US 20090056988A1
• Time in Patent Office: Days
• US Class Current: 174/255
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.

Claims

1. A chip package comprising:

a first printed circuit board (PCB) comprising a first pad at a first top side of said first printed circuit board;

a solder ball on a first bottom side of said first printed circuit board;

a first chip over said first top side, wherein said first chip is connected to said first pad;

a second chip over said first chip; and

a portion over said first top side and over said first and second chips, wherein said portion comprises a second printed circuit board over said first top side and over said first and second chips, a third chip over a second top side of said second printed circuit board, a first metal bump having a top end on a first region of a second bottom side of said second printed circuit board and a bottom end on said first top side, and a second metal bump having a top end on a second region of said second bottom side and a bottom end on said first top side, wherein said first top side faces said second bottom side, wherein said second printed circuit board comprises a second pad at said second top side, wherein said third chip is connected to said second pad, wherein said first and second chips are between said first and second metal bumps, and wherein said first and second chips are between said first top side and a third region of said second bottom side, wherein said third region is directly over said second chip, and wherein said third region is between said first and second regions, and said first, second and third regions are at a substantially same horizontal level.

2. The chip package of claim 1 further comprising a third metal bump between said first chip and said first pad.

3. The chip package of claim 1 further comprising a solder between said first chip and said first pad.

4. The chip package of claim 1, wherein said portion further comprises a third metal bump between said third chip and said second pad.

5. The chip package of claim 1, wherein said portion further comprises a solder between said third chip and said second pad.

6. The chip package of claim 1, wherein said portion further comprises a capacitor on said second printed circuit board.

7. The chip package of claim 1, wherein said first metal bump comprises a solder.

8. A chip package comprising:

a first printed circuit board (PCB) comprising a first pad at a first top side of said first printed circuit board;

a solder ball on a first bottom side of said first circuit printed circuit board;

a first chip over said first top side, wherein said first chip is connected to said first pad;

a second chip over said first chip;

a second printed circuit board over said first top side and over said first and second chips, wherein said second printed circuit board comprises a second pad at a second top side of said second printed circuit board, and wherein said first and second chips are between said first top side and a first region of a second bottom side of said second printed circuit board, wherein said second bottom side faces said first top side, and wherein said first region is directly over said second chip;

a first metal bump having a top end on a second region of said second bottom side and a bottom end on said first top side;

a second metal bump having a top end on a third region of said second bottom side and a bottom end on said first top side, wherein said first and second chips are between said first and second metal bumps, and wherein said first region is between said second and third regions, and said first, second and third regions are at a substantially same horizontal level;

a third chip over said second top side, wherein said third chip is connected to said second pad; and

a fourth chip over said third chip, wherein a vertical distance between said third and fourth chips is less than a thickness of said second printed circuit board.

9. The chip package of claim 8 further comprising a third metal bump between said first chip and said first pad.

10. The chip package of claim 8 further comprising a solder between said first chip and said first pad.

11. The chip package of claim 8 further comprising a third metal bump between said third chip and said second pad.

12. The chip package of claim 8 further comprising a solder between said third chip and said second pad.

13. The chip package of claim 8 further comprising a third printed circuit board over said second top side and over said third and fourth chips, and a third metal bump having a top end on a third bottom side of said third printed circuit board and a bottom end on said second top side.

14. The chip package of claim 8, wherein said first metal bump comprises a solder.

15. A chip package comprising:

a portion comprising a first printed circuit board (PCB), a solder ball on a first bottom side of said first printed circuit board, and a first chip over a first top side of said first printed circuit board, wherein said first chip is connected to a first pad of said first printed circuit board, wherein said first pad is at said first top side;

a second printed circuit board over said first top side and over said first chip, wherein said second printed circuit board comprises a second pad at a second top side of said second printed circuit board, and wherein said first chip is between said first top side and a first region of a second bottom side of said second printed circuit board, wherein said second bottom side faces said first top side, and wherein said first region is directly over said first chip;

a first metal bump having a top end on a second region of said second bottom side and a bottom end on said first top side;

a second metal bump having a top end on a third region of said second bottom side and a bottom end on said first top side, wherein said first chip is between said first and second metal bumps, and wherein said first region is between said second and third regions, and said first, second and third regions are at a substantially same horizontal level;

a second chip over said second top side, wherein said second chip is connected to said second pad; and

a third chip over said second chip, wherein a vertical distance between said second and third chips is less than a thickness of said second printed circuit board.

16. The chip package of claim 15, wherein said portion further comprises a third metal bump between said first chip and said first pad.

17. The chip package of claim 15, wherein said portion further comprises a solder between said first chip and said first pad.

18. The chip package of claim 15 further comprising a third metal bump between said second chip and said second pad.

19. The chip package of claim 15 further comprising a solder between said second chip and said second pad.

20. The chip package of claim 15, wherein said first metal bump comprises a solder.