Semiconductor device

• US 20090057722A1
• Filed: 09/19/2008
• Published: 03/05/2009
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG), Tohoku University National Universities Corporation
• Original Assignee: Tohoku University National Universities Corporation, Unisantis Electronics Japan Ltd.
• Inventors: Masuoka, Fujio, Nakamura, Hiroki
• Granted Patent: US 8,039,893 B2
• Time in Patent Office: Days
• US Class Current: 257/207
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n−1th output terminal is connected with an nth input terminal.

Claims

1. A semiconductor device comprising a CMOS inverter coupling circuit that couples n (n is two or above) CMOS inverters with each other,

each of the n CMOS inverters having:

a first MOS transistor for a first conductivity type channel, which has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer;

a second MOS transistor for a second conductivity type channel different from the first conductivity type channel, which has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the CMOS inverter arranged so as to connect the gate of the first MOS transistor with the gate of the second MOS transistor;

an output terminal of the CMOS inverter arranged so as to connect a drain diffusion layer of the first MOS transistor with a drain diffusion layer of the second MOS transistor in an island-shaped semiconductor lower layer;

a power supply wiring line for the first MOS transistor, which is arranged on a source diffusion layer of the first MOS transistor;

a power supply wiring line for the second MOS transistor, which is arranged on a source diffusion layer of the second MOS transistor,

wherein the semiconductor device further has a coupling portion that is used to connect the output terminal of an n−

1th CMOS inverter with the input terminal of an nth CMOS inverter when arranging each of the n CMOS inverters with respect to the substrate, and the coupling portion is arranged between the substrate and the power supply wiring line for the first MOS transistor.

2. The semiconductor device according to claim 1, wherein, when the n CMOS inverters are arranged in a row with respect to the substrate,

the first MOS transistor of the n−

1th CMOS inverter and the first MOS transistor of the nth CMOS inverter are arranged to be adjacent to each other,

the second MOS transistor of the nth CMOS inverter and the second MOS transistor of the n+1th CMOS inverter are arranged to be adjacent to each other,

the power supply wiring line for the first MOS transistor of the n−

1th CMOS inverter is connected with the power supply wiring line for the first MOS transistor of the nth CMOS inverter on the source diffusion layers, and

the power supply wiring line for the second MOS transistor of the nth CMOS inverter is connected with the power supply wiring line for the second MOS transistor of the n+1th CMOS inverter on the source diffusion layers.

3. The semiconductor device according to claim 1, wherein the n CMOS inverters arranged in a row with respect to the substrate are arranged in m rows (m is two or above) with respect to the substrate,

the power supply wiring lines for the first MOS transistors of the respective CMOS inverters are connected with each other on the source diffusion layers, and

the power supply wiring lines for the second MOS transistors of the respective CMOS inverters are connected with each other on the source diffusion layers.

4. The semiconductor device according to claim 2, wherein the n CMOS inverters arranged in a row with respect to the substrate are arranged in m rows (m is two or above) with respect to the substrate,

the power supply wiring lines for the first MOS transistors of the respective CMOS inverters are connected with each other on the source diffusion layers, and

the power supply wiring lines for the second MOS transistors of the respective CMOS inverters are connected with each other on the source diffusion layers.

5. The semiconductor device according to claim 1, wherein the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is an n-channel transistor.

6. The semiconductor device according to claim 2, wherein the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is an n-channel transistor.

7. The semiconductor device according to claim 3, wherein the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is an n-channel transistor.

8. The semiconductor device according to claim 4, wherein the first MOS transistor is a p-channel MOS transistor, and the second MOS transistor is an n-channel transistor.

9. The semiconductor device according to claim 1, wherein the first MOS transistor is an n-channel MOS transistor, and the second MOS transistor is an n-channel MOS transistor.

10. The semiconductor device according to claim 2, wherein the first MOS transistor is an n-channel MOS transistor, and the second MOS transistor is an n-channel MOS transistor.

11. The semiconductor device according to claim 3, wherein the first MOS transistor is an n-channel MOS transistor, and the second MOS transistor is an n-channel MOS transistor.

12. The semiconductor device according to claim 4, wherein the first MOS transistor is an n-channel MOS transistor, and the second MOS transistor is an n-channel MOS transistor.

13. The semiconductor device according to claim 1, wherein the first MOS transistor is an n-channel MOS transistor, the second MOS transistor is a p-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

14. The semiconductor device according to claim 2, wherein the first MOS transistor is an n-channel MOS transistor, the second MOS transistor is a p-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

15. The semiconductor device according to claim 3, wherein the first MOS transistor is an n-channel MOS transistor, the second MOS transistor is a p-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

16. The semiconductor device according to claim 4, wherein the first MOS transistor is an n-channel MOS transistor, the second MOS transistor is a p-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

17. The semiconductor device according to claim 1, wherein the first MOS transistor is a p-channel MOS transistor, the second MOS transistor is an n-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

18. The semiconductor device according to claim 2, wherein the first MOS transistor is a p-channel MOS transistor, the second MOS transistor is an n-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

19. The semiconductor device according to claim 3, wherein the first MOS transistor is a p-channel MOS transistor, the second MOS transistor is an n-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

20. The semiconductor device according to claim 4, wherein the first MOS transistor is a p-channel MOS transistor, the second MOS transistor is an n-channel MOS transistor, and the number of the p-channel MOS transistors is double the number of the n-channel transistors.

21. An n-channel MOS transistor, which is used in the semiconductor device according to claim 5 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

22. An n-channel MOS transistor, which is used in the semiconductor device according to claim 6 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

23. An n-channel MOS transistor, which is used in the semiconductor device according to claim 7 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

24. An n-channel MOS transistor, which is used in the semiconductor device according to claim 8 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

25. An n-channel MOS transistor, which is used in the semiconductor device according to claim 9 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

26. An n-channel MOS transistor, which is used in the semiconductor device according to claim 10 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

27. An n-channel MOS transistor, which is used in the semiconductor device according to claim 11 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

28. An n-channel MOS transistor, which is used in the semiconductor device according to claim 12 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

29. An n-channel MOS transistor, which is used in the semiconductor device according to claim 13 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

30. An n-channel MOS transistor, which is used in the semiconductor device according to claim 14 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

31. An n-channel MOS transistor, which is used in the semiconductor device according to claim 15 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

32. An n-channel MOS transistor, which is used in the semiconductor device according to claim 16 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

33. An n-channel MOS transistor, which is used in the semiconductor device according to claim 17 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

34. An n-channel MOS transistor, which is used in the semiconductor device according to claim 18 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

35. An n-channel MOS transistor, which is used in the semiconductor device according to claim 19 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

36. An n-channel MOS transistor, which is used in the semiconductor device according to claim 20 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

37. A p-channel MOS transistor, which is used in the semiconductor device according to claim 5 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

38. A p-channel MOS transistor, which is used in the semiconductor device according to claim 6 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

39. A p-channel MOS transistor, which is used in the semiconductor device according to claim 7 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

40. A p-channel MOS transistor, which is used in the semiconductor device according to claim 8 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

41. A p-channel MOS transistor, which is used in the semiconductor device according to claim 9 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

42. A p-channel MOS transistor, which is used in the semiconductor device according to claim 10 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

43. A p-channel MOS transistor, which is used in the semiconductor device according to claim 11 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

44. A p-channel MOS transistor, which is used in the semiconductor device according to claim 12 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

45. A p-channel MOS transistor, which is used in the semiconductor device according to claim 13 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

46. A p-channel MOS transistor, which is used in the semiconductor device according to claim 14 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

47. A p-channel MOS transistor, which is used in the semiconductor device according to claim 15 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

48. A p-channel MOS transistor, which is used in the semiconductor device according to claim 16 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

49. A p-channel MOS transistor, which is used in the semiconductor device according to claim 17 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

50. A p-channel MOS transistor, which is used in the semiconductor device according to claim 18 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

51. A p-channel MOS transistor, which is used in the semiconductor device according to claim 19 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

52. A p-channel MOS transistor, which is used in the semiconductor device according to claim 20 and has a structure in which a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

a drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

53. A semiconductor device comprising a CMOS inverter coupling circuit in which CMOS inverters on at least two stages are coupled with each other, the CMOS inverter having a first CMOS inverter and a second CMOS inverter,

wherein the first CMOS inverter is a CMOS inverter having:

an n-channel semiconductor device having a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer;

a p-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the first CMOS inverter arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the first CMOS inverter arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in an island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with a source diffusion layer of the p-channel semiconductor device,

the second CMOS inverter is a CMOS inverter having;

an n-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

a p-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the second CMOS inverter arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the second CMOS inverter arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in the island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with a source diffusion layer of the p-channel semiconductor device,

the output terminal of the first CMOS inverter connected with the input terminal of the second CMOS inverter,

the first power supply wiring line connected with the source diffusion layer of the n-channel semiconductor device in the first CMOS inverter is connected with the first power supply wiring line V_SS connected with the source diffusion layer of the n-channel semiconductor device in the second CMOS inverter on the source diffusion layers, and

the second power supply wiring line connected with the source diffusion layer of the p-channel semiconductor device in the first CMOS inverter is connected with the second power supply wiring line connected with the source diffusion layer of the p-channel semiconductor device in the second CMOS inverter on the source diffusion layers.

56. An n-channel semiconductor device, which is used in the semiconductor device according to claim 53 and has a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

59. A p-channel semiconductor device, which is used in the semiconductor device according to claim 53 and has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

54. A semiconductor device comprising a CMOS inverter coupling circuit in which CMOS inverters on at least two stages are coupled with each other, the CMOS inverter having a first CMOS inverter and a second CMOS inverter,

wherein the first CMOS inverter is a CMOS inverter having:

one n-channel semiconductor device having a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor devices each having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the first CMOS inverter arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the first CMOS inverter arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in an island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the second CMOS inverter is a CMOS inverter having;

one n-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor devices each having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the second CMOS inverter arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the second CMOS inverter arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in the island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the output terminal of the first CMOS inverter is connected with the input terminal of the second CMOS inverter,

the first power supply wiring line V_SS connected with the source diffusion layer of the n-channel semiconductor device in the first CMOS inverter is connected with the first power supply wiring line V_SS connected with the source diffusion layer of the n-channel semiconductor device in the second CMOS inverter on the source diffusion layers, and

the second power supply wiring line V_CC connected with the source diffusion layers of the p-channel semiconductor devices in the first CMOS inverter is connected with the second power supply wiring line V_CC connected with the source diffusion layers of the two p-channel semiconductor devices in the second CMOS inverter on the source diffusion layers.

57. An n-channel semiconductor device, which is used in the semiconductor device according to claim 54 and has a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

60. A p-channel semiconductor device, which is used in the semiconductor device according to claim 54 and has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

55. A semiconductor device comprising a CMOS inverter coupling circuit in which CMOS inverters arranged in at least two rows and two columns are coupled with each other,

wherein the CMOS inverter in a first row and a second column is a CMOS inverter having:

one n-channel semiconductor device having a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor devices each having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the CMOS inverter in the first row and the second column, which is arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the CMOS inverter in the first row and the second column, which is arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in an island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the CMOS inverter in the first row and a first column is a CMOS inverter having;

one n-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor devices each having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the CMOS inverter in the first row and the first column, which is arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the CMOS inverter in the first row and the first column, which is arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in the island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the output terminal of the CMOS inverter in the first row and the second column is connected with the input terminal of the CMOS inverter in the first row and the first column in the CMOS inverter coupling circuit,

the CMOS inverter in a second row and the second column is a CMOS inverter having;

one n-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor devices each having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the CMOS inverter in the second row and the second column, which is arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the CMOS inverter in the second row and the second column arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in the island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the CMOS inverter in the second row and the first column is a CMOS inverter having;

one n-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

two p-channel semiconductor device having a structure where a drain, a gate, and a source are arranged in the vertical direction with respect to the substrate and the gate surrounds an island-shaped semiconductor layer;

an input terminal of the CMOS inverter in the second row and the first column, which is arranged so as to connect the gate of the n-channel semiconductor device with the gate of the p-channel semiconductor device;

an output terminal of the CMOS inverter in the second row and the first column, which is arranged so as to connect a drain diffusion layer of the n-channel semiconductor device with a drain diffusion layer of the p-channel semiconductor device in the island-shaped semiconductor lower layer;

a first power supply wiring line connected with a source diffusion layer of the n-channel semiconductor device; and

a second power supply wiring line connected with source diffusion layers of the two p-channel semiconductor devices,

the output terminal of the CMOS inverter in the second row and the second column is connected with the input terminal of the CMOS inverter in the second row and the first column in the CMOS inverter coupling circuit, and

the first power supply wiring line connected with the source diffusion layer of the n-channel semiconductor device in the CMOS inverter in the first row and the second column;

the first power supply wiring line connected with the source diffusion layer of the n-channel semiconductor device in the CMOS inverter in the first row and the first column;

the first power supply wiring line connected with the source diffusion layer of the n-channel semiconductor device in the CMOS inverter in the second row and the second column; and

the first power supply wiring line V_SS connected with the source diffusion layer of the n-channel semiconductor device of the CMOS inverter in the second row and the first column are connected with each other on the source diffusion layers, and

the second power supply wiring line connected with the source diffusion layers of the two p-channel semiconductor devices in the CMOS inverter in the first row and the second column;

the second power supply wiring line connected with the source diffusion layers of the two p-channel semiconductor devices in the CMOS inverter in the second row and the second column;

the second power supply wiring line connected with the source diffusion layers of the two p-channel semiconductor devices in the CMOS inverter in the first row and the first column; and

the second power supply wiring line connected with the source diffusion layers of the two p-channel semiconductor devices in the CMOS inverter in the second row and the first column are connected with each other on the source diffusion layers.

58. An n-channel semiconductor device, which is used in the semiconductor device according to claim 55 and has a structure where a drain, gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.

61. A p-channel semiconductor device, which is used in the semiconductor device according to claim 55 and has a structure where a drain, a gate, and a source are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer,

wherein insulating film layers are formed above and below the gate,

a polysilicon wiring line surrounds a part of a drain diffusion layer in an island-shaped semiconductor lower layer,

the drain diffusion layer, the polysilicon wiring line, the gate, and a source diffusion layer are salicided, and

a metal wiring line is formed on the source diffusion layer.