Shielded Gate Trench FET with the Shield and Gate Electrodes Connected Together in Non-active Region

• US 20090057754A1
• Filed: 11/11/2008
• Published: 03/05/2009
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Christopher Boguslaw Kocon, Nathan Kraft, Paul Thorup
• Inventors: Thorup, Paul, Kocon, Christopher Boguslaw, Kraft, Nathan
• Granted Patent: US 7,859,047 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.

Claims

1. A field effect transistor (FET) comprising:

a plurality of trenches extending into a semiconductor region;

a shield electrode in a lower portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

an inter-electrode dielectric (IED) over the shield electrode in each trench;

a body region extending between each pair of adjacent trenches;

a gate electrode recessed in an upper portion of each trench over the IED, the gate electrode being insulated from corresponding body regions by a gate dielectric;

source regions in each body region adjacent to the trenches, the source regions having a conductivity type opposite to that of the body regions;

a first interconnect layer contacting the source and body regions; and

a dielectric material insulating each gate electrode and the second interconnect layer from one another,

wherein the plurality of trenches extend in an active region of the FET, the shield electrode and gate electrode extending out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer, and the electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.

2. The FET of claim 1 further comprising:

a substrate; and

a drift region bounded by the body regions and the substrate, wherein the plurality of trenches terminate within the drift region.

3. The FET of claim 1 further comprising:

a substrate; and

a drift region bounded by the body regions and the substrate, wherein the plurality of trenches extend through the drift region and terminate within the substrate.

4. The FET of claim 1 wherein the shield electrode and the gate electrode in each trench are electrically connected together by an additional connection through the IED in each trench.

5. The FET of claim 1 wherein the first interconnect layer is a source interconnect layer, and the second interconnect layer is a gate interconnect layer.