Trench MOSFET with Trench Termination and manufacture thereof

• US 20090057756A1
• Filed: 09/26/2007
• Published: 03/05/2009
• Est. Priority Date: 09/26/2006
• Status: Active Grant

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force-Mos Technology Corporation (Force Mos Technology Co., Ltd.)
• Inventors: Hshieh, Fwu-Iuan
• Granted Patent: US 7,750,398 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with a trench termination, including a substrate including a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region; a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET; a plurality of metal contact plugs connected to respective metal layer regions; a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; a margin terminating gate trench which is around the gate trenches; and a margin terminating active region which is formed underneath the margin terminating gate trench.

Claims

1. A trench MOSFET with a trench termination, comprising:

a substrate comprising a drain region which is strongly doped and a doping epi layer region, which is weekly doped the same type as the drain region, on the drain region;

a plurality of source and body regions formed in the epi layer;

a metal layer comprising a plurality of metal layer regions which are connected to respective source and body, and gate regions forming metal connections of the MOSFET;

a plurality of metal contact plugs connected to respective metal layer regions;

a plurality of gate trenches filled with polysilicon to form a plurality of trenched gates on top of epi layer;

an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions;

a margin terminating gate trench which is around the gate trenches; and

a margin terminating active region which is formed underneath the margin terminating gate trench.

2. The trench MOSFET as claimed in claim 1, wherein further comprises a margin terminating sidewall channel region formed at a side of the margin terminating gate trench, and a margin terminating sidewall source region formed on the margin terminating sidewall channel region.

3. The trench MOSFET as claimed in claim 1, wherein the metal layer comprises a first metal layer region and a second metal layer region which are both formed on the top of the MOSFET structure to be the source metal, and the gate and field plate metal of the MOSFET respectively.

4. The trench MOSFET as claimed in claim 3, wherein the second metal layer region is divided into two parts which are the gate runner and the field plate metal of the MOSFET respectively.

5. The trench MOSFET as claimed in claim 1, wherein the MOSFET structure comprises a plurality of transistors formed in a N-type doping epi region which is weekly n-doped on a substrate which is strongly n-doped.

6. The trench MOSFET as claimed in claim 1, wherein the insulating layer is made of a silicon dioxide layer or a combination of silicon dioxide and a silicon nitride layer.

7. A method for manufacturing a trench MOSFET with a trench termination, comprising the following steps:

providing an epi layer on heavily doped substrate;

forming a plurality of trenches in the epi layer;

covering a gate oxide layer on the sidewalls and bottom of the trenches;

forming a conductive layer in the trenches to be used as the gate of MOSFET;

forming a plurality of channel regions and source regions according to active regions of the trench MOSFET in the epi layer, and a plurality of channel regions and source regions according to termination regions of the trench MOSFET in the epi layer;

forming an insulating layer on the epi layer;

forming a plurality of contact openings in the insulating layer and the source and body regions; and

forming metal contact plugs in the contact openings to directly contact with both source and body regions, and a metal layer on the insulating layer.

8. The method as claimed in claim 7, wherein further comprises a margin terminating sidewall channel region formed at a side of the margin terminating gate trench, and a margin terminating sidewall source region formed on the margin terminating sidewall channel region.

9. The method as claimed in claim 7, wherein the metal layer comprises a first metal layer region and a second metal layer region which are both formed on the top of the MOSFET structure to be the source metal, and the gate and field plate metal of the MOSFET respectively.

10. The method as claimed in claim 9, wherein the second metal layer region is divided into two parts which are the gate runner and the field plate metal of the MOSFET respectively.

11. The method as claimed in claim 7, wherein the MOSFET structure comprises a plurality of transistors formed in a N-type doping epi region which is weekly n-doped on a substrate which is strongly n-doped.

12. The method as claimed in claim 7, wherein the insulating layer is made of a silicon dioxide layer or a combination of silicon dioxide and a silicon nitride layer.