SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090057771A1
• Filed: 09/04/2008
• Published: 03/05/2009
• Est. Priority Date: 09/05/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fukasaku, Katsuhiko
• Granted Patent: US 7,939,895 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

Disclosed herein is a semiconductor device including a semiconductor substrate provided with an N-type FET and P-type FET, with a gate electrode of the N-type FET and a gate electrode of the P-type FET having undergone full-silicidation, wherein the gate electrode of the P-type FET has such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of the semiconductor substrate, and the gate electrode of the N-type FET has such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of the semiconductor substrate.

Claims

1. A semiconductor device comprising

a semiconductor substrate provided with an N-type field effect transistor and P-type field effect transistor,

with a gate electrode of said N-type field effect transistor and a gate electrode of said P-type field effect transistor having undergone full-silicidation,

wherein said gate electrode of said P-type field effect transistor has such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of said semiconductor substrate, and

said gate electrode of said N-type field effect transistor has such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of said semiconductor substrate.

3. The semiconductor device as set forth in claim 1, wherein said gate electrode of said P-type field effect transistor includes Ni₃Si.

4. The semiconductor device as set forth in claim 1, wherein said gate of said N-type field effect transistor includes NiSi₂.

2. A semiconductor device comprising

a semiconductor substrate provided with an N-type field effect transistor and a P-type field effect transistor,

with a gate electrode of said N-type field effect transistor and a gate electrode of said P-type field effect transistor having undergone full-silicidation,

wherein said gate electrode of said P-type field effect transistor has a section having a forwardly tapered shape in relation to a surface of said semiconductor substrate, and

said gate electrode of said N-type field effect transistor has a section having a reversely tapered shape in relation to the surface of said semiconductor substrate.

5. A method of manufacturing a semiconductor device in which, at the time of providing a semiconductor substrate with an N-type field effect transistor and a P-type field effect transistor,

a gate electrode of said N-type field effect transistor and a gate electrode of said P-type field effect transistor are subjected to full-silicidation, the method comprising the steps of:

forming said gate electrode of said P-type field effect transistor into such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of said semiconductor substrate;

forming said gate electrode of said N-type field effect transistor into such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of said semiconductor substrate;

thereafter forming a mask over said gate electrode of said P-type field effect transistor and subjecting only said gate of said N-type field effect transistor to full-silicidation; and

forming a mask over said gate electrode of said N-type field effect transistor and subjecting only said gate electrode of said P-type field effect transistor to full-silicidation.