INDUCTOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20090057824A1
• Filed: 08/27/2008
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Kwak, Sung-Ho
• Granted Patent: US 7,786,586 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An inductor of a semiconductor device and a method for manufacturing the same are disclosed. The inductor has a spiral structure, and includes a semiconductor substrate formed with a sub-structure. At least one metal line layer may be formed over the semiconductor substrate. At least one inductor line layer may be formed over the metal line layer. A space layer may be formed between the inductor line layer and the semiconductor substrate.

Claims

1. An apparatus comprising:

a semiconductor substrate formed with a sub-structure;

at least one metal line layer formed over the semiconductor substrate;

at least one inductor line layer formed over the metal line layer; and

a space layer formed between the inductor line layer and the semiconductor substrate.

2. The apparatus of claim 1, wherein said at least one metal line layer comprises:

a lower metal line layer formed over the semiconductor layer; and

an upper metal line layer formed over the lower metal line layer.

3. The apparatus of claim 2, wherein the upper metal line layer comprises a plurality of metal line layers.

4. The apparatus of claim 2, wherein the lower metal line layer comprises:

a lower insulating film formed over an entire upper surface of the semiconductor substrate;

a lower hole formed on a first side of the lower insulating film;

a lower photoresist layer formed in the lower hole;

a silylation film formed over the lower photoresist layer;

a lower via hole formed on a second side of the lower insulating film; and

a lower metal line buried in the lower via hole.

5. The apparatus of claim 2, wherein the upper metal line layer comprises:

an upper insulating film formed over an entire upper surface of the semiconductor substrate including the lower metal line layer;

an upper hole formed in a first side of the upper insulating film;

an upper photoresist layer formed in the upper hole;

an upper silylation film formed over the upper photoresist layer;

an upper via hole formed in a second side of the upper insulating film; and

an upper metal line buried in the upper via hole.

6. The apparatus of claim 4, wherein the upper metal line layer comprises:

an upper insulating film formed over an entire upper surface of the lower insulating film including the lower silylation film and the lower metal line;

an upper hole formed in a first side of the upper insulating film to expose the lower photoresist layer;

an upper photoresist layer formed in the upper hole;

an upper silylation film formed over the upper photoresist layer;

an upper via hole formed in a second side of the upper insulating film; and

an upper metal line buried in the upper via hole.

7. The apparatus of claim 1, wherein the inductor line layer comprises:

an insulating film formed over the metal line layer;

an inductor hole formed in the insulating film; and

an inductor line buried in the inductor hole.

8. The apparatus of claim 7, wherein the inductor line has a spiral structure.

9. A method comprising:

preparing a semiconductor substrate formed with an sub-structure;

forming at least one metal line layer over the semiconductor substrate;

forming at least one inductor line layer over the metal line layer; and

forming a space layer beneath the inductor metal line layer.

10. The method of claim 9, wherein said forming at least one metal line layer over the semiconductor substrate comprises:

forming a lower metal line layer over the semiconductor substrate; and

forming an upper metal line layer over the lower metal line layer.

11. The method of claim 10, wherein the upper metal line layer comprises a plurality of metal line layers.

12. The method of claim 10, wherein said forming the lower metal line layer over the semiconductor substrate comprises:

forming a lower insulating film over an entire upper surface of the semiconductor substrate;

patterning the lower insulating film on a first side of the lower insulating film, thereby forming a lower hole;

forming a lower photoresist layer formed in the lower hole;

silylating the lower photoresist layer, thereby forming a lower silylation film;

patterning the lower insulating film on a second side of the lower insulating film, thereby forming a lower via hole;

forming a lower metal layer over an entire upper surface of the lower insulating film including the lower via hole and the lower silylation film; and

subjecting the lower metal layer to a chemical mechanical polishing process such that the lower silylation film is exposed, thereby forming a lower metal line.

13. The method of claim 12, wherein the lower metal layer is formed by an electro-chemical plating process.

14. The method of claim 10, wherein said forming the upper metal line layer over the lower metal line layer comprises:

forming an upper insulating film over an entire upper surface of the semiconductor substrate including the lower metal line layer;

patterning the upper insulating film on a first side of the upper insulating film, thereby forming an upper hole;

forming an upper photoresist layer in the upper hole;

silylating the upper photoresist layer, thereby forming an upper silylation film;

patterning the upper insulating film on a second side of the upper insulating film, thereby forming an upper via hole;

forming an upper metal layer over an entire upper surface of the upper insulating film including the upper via hole and the upper silylation film; and

subjecting the upper metal layer to a chemical mechanical polishing process such that the upper silylation film is exposed, thereby forming an upper metal line.

15. The method of claim 12, wherein said forming the upper metal line layer over the lower metal line layer comprises:

forming an upper insulating film over an entire upper surface of the lower insulating film including the lower silylation film and the lower metal line;

patterning the upper insulating film on a first side of the upper insulating film such that the lower photoresist layer is exposed, thereby forming an upper hole;

forming an upper photoresist layer in the upper hole;

silylating the upper photoresist layer, thereby forming an upper silylation film;

patterning the upper insulating film on a second side of the upper insulating film, thereby forming an upper via hole;

forming an upper metal layer over an entire upper surface of the upper insulating film including the upper via hole and the upper silylation film; and

subjecting the upper metal layer to a chemical mechanical polishing process such that the upper silylation film is exposed, thereby forming an upper metal line.

16. The method of claim 15, wherein the upper metal layer is formed by an electro-chemical plating process.

17. The method of claim 15, wherein said forming at least one inductor line layer over the metal line layer comprises:

forming an insulating film over the metal line layer;

patterning the insulating film, thereby forming an inductor hole; and

forming an inductor metal layer over an entire upper surface of the insulating film such that the inductor metal layer fills the inductor hole; and

subjecting the inductor metal layer to a chemical mechanical polishing process, thereby forming an inductor line.

18. The method of claim 17, wherein said forming the space layer beneath the inductor metal line layer comprises:

patterning the insulating film, the upper silylation film, and the photoresist layers, thereby forming a photoresist removing hole extending to a portion of the lower photoresist layer through the insulating film and the upper silylation film; and

wet etching the photoresist layers through the photoresist removing hole, to remove the photoresist layers, thereby forming the space layer.

19. The method of claim 18, wherein the inductor line is patterned to have a spiral structure.

20. The method of claim 19, wherein the inductor metal layer is made of one of copper and aluminum.