INTERCONNECT IN A MULTI-ELEMENT PACKAGE

• US 20090057849A1
• Filed: 08/29/2007
• Published: 03/05/2009
• Est. Priority Date: 08/29/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Tang, Jinbang, Lytle, William H., Frear, Darrel R.
• Granted Patent: US 7,838,420 B2
• Time in Patent Office: Days
• US Class Current: 257/664
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A packaged semiconductor device includes an interconnect layer over a first side of a polymer layer, a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer, a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side, and a connector block within the polymer layer. The connector block has at least one electrical path extending from a first surface of the connector block to a second surface of the connector block. The at least one electrical path electrically couples the interconnect layer to the first conductive element. A method of forming the packaged semiconductor device is also described.

Claims

1. A packaged semiconductor device comprising:

an interconnect layer over a first side of a polymer layer;

a semiconductor device surrounded on at least three sides by the polymer layer and coupled to the interconnect layer;

a first conductive element over a second side of the polymer layer, wherein the second side is opposite the first side; and

a connector block within the polymer layer, having at least one electrical path extending from a first surface of the connector block to a second surface of the connector block, and electrically coupling the interconnect layer to the first conductive element through the at least one electrical path.

2. The packaged semiconductor device of claim 1, wherein the connector block comprises an insulating material surrounding the at least one electrical path.

3. The packaged semiconductor device of claim 1, wherein the connector block has at least two coaxial electrical paths.

4. The packaged semiconductor device of claim 1, wherein the at least one electrical path is a ground path and the first conductive element is a ground plane.

5. The packaged semiconductor device of claim 1, wherein the at least one electrical path is a signal path and the first conductive element is an antenna.

6. The packaged semiconductor device of claim 5, further comprising a second conductive element and a second electrical path, wherein the second electrical path is a ground path and the second conductive element is a ground plane.

7. The packaged semiconductor device of claim 6, further comprising a third electrical path,

wherein the third electrical path is coupled to the antenna.

8. A method for forming a packaged semiconductor device, the method comprising:

surrounding a semiconductor device on at least three sides by a polymer layer;

forming an interconnect layer over a first side of the polymer layer and over the semiconductor device, wherein the semiconductor device is coupled to the interconnect layer;

forming a conductive element over a second side of the polymer layer, wherein the second side is opposite the first side; and

electrically coupling the interconnect layer to the conductive element through a connector block within the polymer layer, having at least one electrical path.

9. The method of claim 8, wherein forming the conductive element over a second side comprises plating a conductive material to form an antenna.

10. The method of claim 8, wherein:

surrounding a semiconductor device on at least three sides by the polymer layer, comprises;

attaching a semiconductor device to a temporary support structure;

forming the polymer layer over the semiconductor device; and

removing the temporary support structure after forming the polymer layer; and

electrically coupling the interconnect layer, comprises;

attaching the connector block to the temporary support structure before forming the polymer layer;

removing a portion of the polymer layer to expose a surface of the connector block; and

forming the interconnect layer over the surface of the connector block while forming the interconnect layer over the first side of the polymer layer.

11. The method of claim 10, further comprising:

depositing a dielectric layer over the surface of the connector block; and

forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the conductive element.

12. The method of claim 8, wherein the at least one electrical path is selected from the group consisting of a ground path and a signal path.

13. The method of claim 8, wherein the first conductive element is selected from a group consisting of a ground plane and an antenna.

14. The method of claim 8, wherein the at least one electrical path comprises at least two coaxial electrical paths.

15. A method for forming a packaged semiconductor device, the method comprising:

attaching a semiconductor device to a temporary support structure;

attaching a connector block to the temporary support structure, wherein the connector block has at least one electrical path;

forming an encapsulant over the connector block and the semiconductor device;

removing a portion of the encapsulant to expose a top surface of the connector block;

forming an interconnect layer electrically coupled to the top surface of the connector block;

removing the temporary support structure to expose a bottom surface of the connector block; and

electrically coupling a tangible element to the bottom surface of the connector block.

16. The method of claim 15, wherein electrically coupling a tangible element to the bottom surface of the connector block, comprises plating a conductive material to form an antenna.

17. The method of claim 16, wherein electrically coupling a tangible element to the bottom surface of the connector block further comprises:

depositing a dielectric layer over the bottom surface of the connector block; and

forming a via in the dielectric layer, wherein the via is electrically coupled to the connector block and the antenna.

18. The method of claim 15, wherein the removing a portion of the encapsulant to expose a top surface of the connector block comprises grinding the encapsulant.

19. The method of claim 15, wherein the temporary support structure is selected from a group consisting of a tape and a carrier.

20. The method of claim 15, wherein the connector block has at least two coaxial electrical paths.