CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION

• US 20090057869A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Abandoned Application

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Liu, Kai, Bhalla, Anup, Sun, Ming, Zhang, Xiaotian, Hebert, Francois
• Application Number:
  US11/849,160
• Publication Number:
  US 20090057869A1
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40247 Connecting the strap to a bond pad of the item
• CPC Class Codes: H01L 2224/4103 Connectors having different sizes
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49051 : Connectors having different shapes
• CPC Class Codes: H01L 2224/49111 : the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49112 : the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/49171 : Fan-out arrangements
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 2224/85205 : Ultrasonic bonding
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A circuit package assembly is disclosed. The assembly includes a conductive substrate; a high-side n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a source on a side facing a surface of the conductive substrate and in electrical contact therewith and a low-side standard n-channel metal oxide semiconductor field effect transistor (NMOSFET) having a drain on a side facing the conductive substrate and in electrical contact therewith. Co-packaging of high-side and low-side NMOSFETs in this manner may reduce package size and parasitic inductance and capacitance compared to conventional packaging.

Claims

1. A circuit package assembly, comprising:

a common die pad;

a first vertical n-channel metal oxide semiconductor field effect transistor (NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith;

a second vertical n-channel metal oxide semiconductor field effect transistor (NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith.

2. The circuit package assembly of claim 1 wherein the first NMOSFET is a high-side NMOSFET and wherein the second NMOSFET is a low-side NMOSFET

3. The circuit package assembly of claim 2 wherein the high-side NMOSFET comprises a bottom source n-channel lateral double diffused MOSFET (LDMOSFET) and wherein the low-side NMOSFET comprises a bottom drain n-channel vertical double diffused MOSFET (VDMOSFET).

4. The circuit package assembly of claim 2, wherein a gate pad and a drain pad of the high-side NMOSFET are located on a side of the high-side NMOSFET facing away from the common die pad, and wherein the gate pad and drain pad are electrically connected to gate and drain leads respectively.

5. The circuit package assembly of claim 1, wherein a gate pad and a source pad of the second NMOSFET are electrically connected to gate and source leads respectively through a plurality of bond wires.

6. The circuit package assembly of claim 2, wherein a drain pad of the high-side NMOSFET and a source pad of the low-side NMOSFET are located on a side of the high-side NMOSFET and the low-side NMOSFET respectively facing away from the common die pad, and wherein the drain pad and source pad are electrically connected to drain and source leads through first and second bond plates respectively.

7. The circuit package assembly of claim 6, wherein the first bond plate includes a first plurality of dimples formed thereon coupling the drain lead to a drain pad on the high-side NMOSFET, the dimples being positioned for contact with the drain pad and wherein the second bond plate includes a second plurality of dimples formed thereon coupling the source lead to a source pad on the low-side NMOSFET, the dimples being positioned for contact with the source pad.

8. The circuit package assembly of claim 7, wherein the first and second pluralities of dimples are soldered respectively to the drain pad and the source pad.

9. The circuit package assembly of claim 8, wherein a gate pad of the high-side NMOSFET and a gate pad of the low-side NMOSFET are electrically connected to gate leads through bond wires or wherein the gate pad of the high-side NMOSFET and the gate pad of the low-side NMOSFET are electrically connected to gate leads through high-side and low-side gate bond plates.

12. The circuit package assembly of claim 2 wherein a drain pad of the high-side NMOSFET located on a side facing away from the common die pad and a source pad of the low-side NMOSFET located on a side facing away from the common die pad are electrically connected to drain and source leads respectively through one or more aluminum power ribbons.

13. The circuit package assembly of claim 12, wherein gate pads of the high-side NMOSFET and the low-side NMOSFET are electrically connected to gate leads through wires, or wherein gate pads of the high-side NMOSFET and the low-side NMOSFET are electrically connected to gate leads through bond plates or power ribbons.

14. The circuit package assembly of claim 2, wherein the high-side NMOSFET is a bottom drain NMOSFET having one or more drain pads on a bottom side and a gate pad and one or more source pads at a top side and is mounted to the common die pad in a “

flipped”

configuration as a “

flip chip”

with the top side proximate to and facing the common die pad, whereby the gate pad and the one or more source pads are proximate to and facing the common die pad.

15. The circuit package assembly of claim 14, wherein the drain pads of the high-side “

flipped”

NMOSFET and one or more source pads of the low-side NMOSFET are electrically connected to corresponding drain and source leads through corresponding high-side and low-side bond plates.

16. The circuit package assembly of claim 12, wherein the “

flip chip”

bond plate includes a plurality of dimples formed thereon adapted to couple the drain lead to the one or more drain pads on the high-side “

flipped”

NMOSFET, the dimples being positioned for contact with the drain pads.

17. The circuit package assembly of claim 16, wherein the high-side “

flipped”

NMOSFET further includes source and gate electrical connections formed using one or more solder balls.

18. The circuit package assembly of claim 17, wherein the low-side source bond plates include a bond plate having a plurality of dimples formed thereon, the bond plate being configured to couple the source lead to source pads on the low-side NMOSFET, the dimples being positioned for contact with the one or more source pads.

19. The circuit package assembly of claim 18, wherein the plurality of dimples on the low-side source bond plate are soldered to the one or more source pads on the low-side NMOSFET and/or wherein a gate of the low-side NMOSFET is electrically connected to a gate lead through a low-side gate bond plate having a dimple formed thereon coupling the gate lead to a corresponding gate pad on the low-side NMOSFET, the dimples being positioned for contact with the gate pad.

20. The circuit package assembly of claim 19, wherein the dimple on the low-side gate bond plate is soldered to the gate pad.

21. The circuit package assembly of claim 14, wherein sources of the low-side NMOSFET are electrically connected to source leads through one or more conductive power ribbons or clips and/or wherein a gate of the low-side NMOSFET is electrically connected to a gate lead through a conductive wire or clip.

22. The circuit package assembly of claim 21, wherein a drain of the high-side “

flipped”

NMOSFET is electrically connected to one or more drain leads through a conductive power ribbon or a conductive clip and/or wherein a gate of the high-side “

flipped”

NMOSFET is electrically connected to a gate lead through a solder ball.

10. The circuit package assembly of claim 10, wherein the high-side gate bond plate includes a dimple formed thereon, the dimple being positioned for contact with the gate pad on the high-side NMOSFET and/or wherein the low-side gate bond plate includes a dimple formed thereon coupling the gate lead to a gate pad on the low-side NMOSFET, the dimple being positioned for contact with the gate pad on the low-side NMOSFET.

11. The circuit package assembly of claim 10, wherein the dimple is soldered to the gate pad on the low-side NMOSFET.

23. A circuit package assembly, comprising:

a common die pad;

a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith, wherein the high-side NMOSFET comprises a bottom source n-channel lateral double diffused MOSFET (LDMOSFET);

a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith, wherein the low-side NMOSFET is a vertical double diffused MOSFET (VDMOSFET).

24. A circuit package assembly, comprising:

a common die pad;

a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith, wherein the high-side NMOSFET is mounted to the common die pad in a “

flipped”

configuration as a “

flip chip”

;

a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith, wherein the low-side NMOSFET is a vertical double diffused MOSFET (VDMOSFET).

25. A circuit package assembly, comprising:

a common die pad;

a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith;

a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith; and

a MOSFET driver integrated circuit (IC) having a high-side gate driver output coupled to a gate of the high-side NMOSFET and a low side gate driver coupled to a gate of the low-side NMOSFET.