POST PASSIVATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND PACKAGING PROCESS FOR SAME

• US 20090057895A1
• Filed: 11/04/2008
• Published: 03/05/2009
• Est. Priority Date: 05/06/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chen, Ke-Hung
• Granted Patent: US 8,558,383 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05173 Rhodium [Rh] as principal constituent
• CPC Class Codes: H01L 2224/05176 Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/05183 Rhenium [Re] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05669 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45155 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/45164 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/45169 : Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/45173 : Rhodium (Rh) as principal constituent
• CPC Class Codes: H01L 2224/45176 : Ruthenium (Ru) as principal constituent
• CPC Class Codes: H01L 2224/45183 : Rhenium (Re) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48639 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48644 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48664 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48669 : Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/48839 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48844 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48847 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48864 : Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/48869 : Platinum (Pt) as principal constituent
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at the surface of the thick support layer, for a next level packaging structure. The thick support layer is planarized before defining the contact structures. The thick support layer may be formed after the conducting posts have been formed, or the thick support layer is formed before forming the conducting posts in vias formed in the thick support layer. An encapsulating layer may be provided above the thick support layer, which top surface is planarized before defining the contact structures. The encapsulating layer and the further support layer may be the same layer.

Claims

1. An integrated circuit chip comprising:

a substrate;

a MOS device on said substrate;

a first contact pad over said substrate;

a second contact pad over said substrate;

a passivation layer over said substrate, wherein a first opening in said passivation layer is over said first contact pad, and said first contact pad has a first contact point at a bottom of said first opening, wherein a second opening in said passivation layer is over said second contact pad, and said second contact pad has a second contact point at a bottom of said second opening, and wherein said passivation layer comprises a nitride;

a metal layer over said passivation layer and on said first and second contact points, wherein said metal layer is connected to said first contact point through said first opening, and said metal layer is connected to said second contact point through said second opening, and wherein said metal layer comprises an adhesion/barrier/seed layer over said passivation layer and on said first and second contact points, and electroplated copper over said adhesion/barrier/seed layer;

a first metal post on said metal layer, wherein said first metal post is connected to said first contact point through said metal layer, wherein the position of said first metal post from a top perspective view is different from that of said first contact point, wherein said first metal post comprises electroplated copper, and wherein said first metal post has a height between 25 and 200 micrometers;

a second metal post on said metal layer, wherein said second metal post is connected to said first contact point through said metal layer, wherein the position of said second metal post from a top perspective view is different from that of said second contact point, wherein said second metal post comprises electroplated copper, wherein said first metal post has a height between 25 and 200 micrometers, and wherein a pitch between said first and second metal posts is less than 250 micrometers;

a first polymer layer over said passivation layer and on said metal layer, wherein said first and second metal posts are in said first polymer layer, and wherein said first polymer layer uncovers a top of said first metal post and a top of said second metal post;

a UBM layer on said top of said first metal post and on said top of said second metal post;

a first electroplated solder bump on said UBM layer and over said top of said first metal post; and

a second electroplated solder bump on said UBM layer and over said top of said second metal post.

2. The integrated circuit chip of claim 1, wherein said UBM layer comprises titanium.

3. The integrated circuit chip of claim 1 further comprising a second polymer layer on said passivation layer, wherein said metal layer and said first polymer layer are on said second polymer layer.

4. The integrated circuit chip of claim 1, wherein said adhesion/barrier/seed layer comprises titanium.

5. The integrated circuit chip of claim 1, wherein said adhesion/barrier/seed layer comprises copper.

6. An integrated circuit chip comprising:

a substrate;

a MOS device on said substrate;

a first contact pad over said substrate;

a second contact pad over said substrate;

a passivation layer over said substrate, wherein a first opening in said passivation layer is over said first contact pad, and said first contact pad has a first contact point at a bottom of said first opening, wherein a second opening in said passivation layer is over said second contact pad, and said second contact pad has a second contact point at a bottom of said second opening, and wherein said passivation layer comprises a nitride;

a metal layer over said passivation layer and on said first and second contact points, wherein said metal layer is connected to said first contact point through said first opening, and said metal layer is connected to said second contact point through said second opening, and wherein said metal layer comprises an adhesion/barrier/seed layer over said passivation layer and on said first and second contact points, and electroplated copper over said adhesion/barrier/seed layer;

a first metal post on said metal layer, wherein said first metal post is connected to said first contact point through said metal layer, wherein the position of said first metal post from a top perspective view is different from that of said first contact point, wherein said first metal post comprises electroplated copper, and wherein said first metal post has a height between 25 and 200 micrometers;

a second metal post on said metal layer, wherein said second metal post is connected to said first contact point through said metal layer, wherein the position of said second metal post from a top perspective view is different from that of said second contact point, wherein said second metal post comprises electroplated copper, wherein said first metal post has a height between 25 and 200 micrometers, and wherein a pitch between said first and second metal posts is less than 250 micrometers; and

a first polymer layer over said passivation layer and on said metal layer, wherein said first and second metal posts are in said first polymer layer, and wherein said first polymer layer uncovers a top of said first metal post and a top of said second metal post.

7. The integrated circuit chip of claim 6 further comprising a second polymer layer on said passivation layer, wherein said metal layer and said first polymer layer are on said second polymer layer.

8. The integrated circuit chip of claim 6, wherein said adhesion/barrier/seed layer comprises titanium.

9. The integrated circuit chip of claim 6, wherein said adhesion/barrier/seed layer comprises copper.

10. The integrated circuit chip of claim 6 further comprising a second polymer layer on said first polymer layer, wherein a third opening in said second polymer layer is over said top of said first metal post, and a fourth opening in said second polymer layer is over said top of said second metal post.

11. An integrated circuit chip having more than 400 pin counts, comprising:

a substrate;

a MOS device on said substrate;

a contact pad over said substrate;

a passivation layer over said substrate, wherein an opening in said passivation layer is over said contact pad, and said contact pad has a contact point at a bottom of said opening, and wherein said passivation layer comprises a nitride;

a metal layer over said passivation layer and on said contact point, wherein said metal layer is connected to said contact point through said opening, and wherein said metal layer comprises an adhesion/barrier/seed layer over said passivation layer and on said first and second contact points, and electroplated copper over said adhesion/barrier/seed layer;

a metal post on said metal layer, wherein said metal post is connected to said contact point through said metal layer, wherein the position of said metal post from a top perspective view is different from that of said contact point, wherein said metal post comprises electroplated copper, and wherein said metal post has a height between 25 and 200 micrometers;

a polymer layer over said passivation layer and on said metal layer, wherein said metal post is in said polymer layer, and wherein said polymer layer uncovers a top of said metal post;

a UBM layer on said top of said metal post; and

an electroplated solder bump on said UBM layer and over said top of said metal post.

12. The integrated circuit chip of claim 11, wherein said UBM layer comprises titanium.

13. The integrated circuit chip of claim 11 further comprising a second polymer layer on said passivation layer, wherein said metal layer and said first polymer layer are on said second polymer layer.

14. The integrated circuit chip of claim 11, wherein said adhesion/barrier/seed layer comprises titanium.

15. The integrated circuit chip of claim 11, wherein said adhesion/barrier/seed layer comprises copper.

16. An integrated circuit chip having more than 400 pin counts, comprising:

a substrate;

a MOS device on said substrate;

a first contact pad over said substrate;

a second contact pad over said substrate;

a passivation layer over said substrate, wherein a first opening in said passivation layer is over said first contact pad, and said first contact pad has a first contact point at a bottom of said first opening, wherein a second opening in said passivation layer is over said second contact pad, and said second contact pad has a second contact point at a bottom of said second opening, and wherein said passivation layer comprises a nitride;

a metal layer over said passivation layer and on said first and second contact points, wherein said metal layer is connected to said first contact point through said first opening, and said metal layer is connected to said second contact point through said second opening, and wherein said metal layer comprises an adhesion/barrier/seed layer over said passivation layer and on said first and second contact points, and electroplated copper over said adhesion/barrier/seed layer;

a first metal post on said metal layer, wherein said first metal post is connected to said first contact point through said metal layer, wherein the position of said first metal post from a top perspective view is different from that of said first contact point, wherein said first metal post comprises electroplated copper, and wherein said first metal post has a height between 25 and 200 micrometers;

a second metal post on said metal layer, wherein said second metal post is connected to said first contact point through said metal layer, wherein the position of said second metal post from a top perspective view is different from that of said second contact point, wherein said second metal post comprises electroplated copper, wherein said first metal post has a height between 25 and 200 micrometers, and wherein a pitch between said first and second metal posts is less than 250 micrometers; and

a polymer layer over said passivation layer and on said metal layer, wherein said first and second metal posts are in said polymer layer, and wherein said polymer layer uncovers a top of said first metal post and a top of said second metal post.

17. The integrated circuit chip of claim 16, wherein said UBM layer comprises titanium.

18. The integrated circuit chip of claim 16 further comprising a second polymer layer on said passivation layer, wherein said metal layer and said first polymer layer are on said second polymer layer.

19. The integrated circuit chip of claim 16, wherein said adhesion/barrier/seed layer comprises titanium.

20. The integrated circuit chip of claim 16, wherein said adhesion/barrier/seed layer comprises copper.