FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY AND METHOD FOR PROGRAMMING

• US 20090058462A1
• Filed: 11/05/2008
• Published: 03/05/2009
• Est. Priority Date: 01/21/2005
• Status: Abandoned Application

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Speers, Theodore, Mason, Martin
• Application Number:
  US12/265,531
• Publication Number:
  US 20090058462A1
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

Claims

1. A method for programming an integrated circuit including a non-volatile memory and a programmable logic unit, the method comprising:

programming device data into a first portion of the non-volatile memory;

programming a user design into the programmable logic unit; and

programming user data into a second portion of the non-volatile memory.

2. The method of claim 1, wherein the device data includes a decryption key, further comprising:

decrypting the user data before programming the user data into the non-volatile memory.

3. The method of claim 1, wherein the device data includes at least one of a serial number and a date code.

4. The method of claim 1, further comprising:

disabling write access to the first portion of the non-volatile memory after programming device data into the first portion of the non-volatile memory.

5. The method of claim 4, further comprising:

disabling read access to the first portion of the non-volatile memory after programming device data into the first portion of the non-volatile memory.

6. The method of claim 1, wherein:

programming user data into a second portion of the non-volatile memory is performed via a TTAG port and a TAP controller circuit disposed on the integrated circuit.

7. A method for programming an integrated circuit including a non-volatile memory and a programmable logic unit, the method comprising:

receiving configuration data for programming the programmable logic unit;

receiving user data for writing into the non-volatile memory;

programming the programmable logic unit with the configuration data; and

writing the user data into the nonvolatile memory.

8. The method of claim 7, further comprising:

receiving an identification of a portion of said non-volatile memory;

receiving a designation of said portion of said non-volatile memory; and

storing said designation for said identified portion of memory.

9. The method of claim 8, wherein the designation is read-only.

10. The method of claim 8, wherein the designation identifies a path through which the identified portion of memory is accessed.

11. The method of claim 10, wherein the path is a JTAG port.

12. The method of claim 10, wherein the path is through programmable logic.

13. The method of claim 10, wherein identification of the path limits access to the identified portion of the non-volatile memory to access only via the identified path.