RADIO FREQUENCY IDENTIFICATION DEVICE HAVING NONVOLATILE FERROELECTRIC MEMORY

• US 20090058616A1
• Filed: 06/27/2008
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KANG, Hee Bok, HONG, Suk Kyoung, AN, Jin Hong
• Granted Patent: US 8,274,369 B2
• Time in Patent Office: Days
• US Class Current: 340/10.500
• CPC Class Codes: H04Q 2209/47 using RFID associated with sensors
• CPC Class Codes: H04Q 2209/84 Measuring functions
• CPC Class Codes: H04Q 9/00 Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom

Abstract

A RFID device having a nonvolatile ferroelectric memory includes an analog block. A power-on reset unit configured to sense a power voltage and output a power sensing signal is included in the analog block. A radio frequency signal sensing unit is configured to sense the level of a detecting signal corresponding to a radio frequency signal received by the antenna of the RFID device and outputs a radio frequency sensing signal. A power-on reset mixer is configured to synthesize the power sensing signal and the radio frequency sensing signal and outputs a power-on reset signal according to the voltage levels of the power sensing signal and the radio frequency sensing signal.

Claims

1. An RFID device having a nonvolatile ferroelectric memory, receiving a radio frequency signal, and generating a power voltage for driving the RFID device, the RFID device comprising:

a power-on reset unit configured to sense the power voltage in order to output a power sensing signal;

a radio frequency signal sensing unit configured to sense a voltage level of a detecting signal corresponding to the radio frequency signal, and outputting a radio frequency sensing signal according to the sensed voltage level; and

a power-on reset mixer configured to receive the power sensing signal and the radio frequency sensing signal, and outputting a power-on reset signal according to the voltage levels of the power sensing signal and the radio frequency sensing signal.

2. The RFID device according to claim 1, wherein the radio frequency signal sensing unit senses a period in which the radio frequency signal is off.

3. The RFID device according to claim 2, wherein the radio frequency signal sensing unit is configured to output the radio frequency sensing signal such that the radio frequency sensing signal remains activated after a maximum period of time in which the detecting signal is inactivated, wherein the radio frequency signal is recognized as a signal during this maximum period of time.

4. The RFID device according to claim 1, wherein the power-on reset mixer outputs the power-on reset signal to be activated when the power sensing signal and the radio frequency sensing signal are activated.

5. The RFID device according to claim 1, wherein the radio frequency signal sensing unit comprises:

a power generating unit configured to adjust an effective resistance in response to a change in the level of the power voltage in order to output a first voltage having a given level;

a delay unit configured to delay the detecting signal for a given time in response to the first voltage in order to output a detecting delay signal; and

a radio frequency signal generating unit configured to perform a logical operation on the detecting signal and the detecting delay signal in order to generate the radio frequency sensing signal.

6. The RFID device according to claim 5, wherein the delay unit comprises:

an inverter chain configured to delay the detecting signal for a given period of time in response to the first voltage and a second voltage;

a first operational amplifier configured to amplify the output signal of the inverter chain at the power voltage level in order to output the detecting delay signal; and

a delay adjusting element connected to the inverter chain and configured to increase a delay time of the falling edge of the detecting signal.

7. The RFID device according to claim 6, wherein the delay adjusting element comprises:

a plurality of delay adjusting resistors each of which is connected between a respective one of the even number inverters of the inverter chain and a second voltage receiving terminal; and

a plurality of delay adjusting capacitors each of which is connected between a respective one of the output terminals of the even number inverters and a ground voltage terminal.

8. The RFID device according to claim 6, wherein the delay unit further comprises a power stabilizing capacitor connected between the first voltage receiving terminal and the ground voltage terminal.

9. The RFID device according to claim 6, wherein the first voltage has a high level and the second voltage has a low level.

10. The RFID device according to claim 5, wherein the radio frequency signal generating unit outputs the radio frequency sensing signal to be activated when the detecting signal and the detecting delay signal are simultaneously at a low level.

11. The RFID device according to claim 5, wherein the radio frequency signal generating unit comprises:

a first logic combination element configured to perform a logical combination of the detecting signal and the detecting delay signal; and

an inverter configured to invert the output signal of the first logic combination element.

12. The RFID device according to claim 11, wherein the first logic combination element is a NOR gate.

13. The RFID device according to claim 11, wherein the radio frequency signal generating unit further comprises a second operational amplifier configured to amplify the output signal of the inverter in order to output the radio frequency sensing signal.

14. The RFID device according to claim 11, wherein the radio frequency signal generating unit further comprises a second current limiting resistor connected between a power voltage receiving terminal and the first logic combination element.

15. The RFID device according to claim 11, wherein the radio frequency signal generating unit further comprises a third current liming resistor connected between the inverter and the ground voltage terminal.

16. The RFID device according to claim 5, wherein the power generating unit comprises:

a positive slope resistance adjusting unit configured to increase a first effective resistance when the voltage level of the power voltage rises; and

a negative slope resistance adjusting unit configured to decrease a second effective resistance when the voltage level of the power voltage rises.

17. The RFID device according to claim 16, wherein the positive slope resistance adjusting unit comprises a plurality of MOS transistors connected in series between a first voltage output terminal and the negative slope resistance adjusting unit.

18. The RFID device according to claim 17, wherein the plurality of MOS transistors are NMOS transistors, and each NMOS transistor has a commonly connected gate and drain.

19. The RFID device according to claim 16, wherein the negative slope resistance adjusting unit comprises a MOS transistor connected between the positive slope resistance adjusting unit and the ground voltage terminal, wherein a gate of the MOS transistor receives the power voltage.

20. The RFID device according to claim 19, wherein the MOS transistor is a NMOS transistor.

21. The RFID device according to claim 16, wherein the power generating unit further comprises a fourth current limiting resistor connected between the power voltage receiving terminal and the positive slope resistance adjusting unit.

22. The RFID device according to claim 1, wherein the power-on reset mixer comprises:

a second logic combination element configured to perform a logical combination of the power sensing signal and the radio frequency sensing signal; and

an inverter configured to invert an output signal of the second logic combination element.

23. The RFID device according to claim 22, wherein the second logic combination element is a NAND gate.