MULTI-PORT DYNAMIC MEMORY METHODS

• US 20090059653A1
• Filed: 11/07/2008
• Published: 03/05/2009
• Est. Priority Date: 01/16/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ji, Brian L., Luk, Wing K.
• Granted Patent: US 7,701,752 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/2209 Concurrent read and write for multi-port memory G11C7/1075
• CPC Class Codes: G11C 2211/4065 Low level details of refresh operations
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output.

Claims

1. A method comprising the steps of:

providing a dynamic random access memory circuit comprising;

at least one write bit line;

at least one read bit line;

a capacitive storage device;

a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line;

a sense amplifier, said sense amplifier being operatively coupled to said at least one read bit line and configured to generate an output signal;

a refresh bypass device, said refresh bypass device being operatively associated with said sense amplifier and said at least one write bit line so as to selectively pass said output signal to said at least one write bit line; and

a write-read bypass device, said write-read bypass device being operatively coupled to said at least one write bit line and said at least one read bit line and being configured to selectively pass a write signal from a write bit line signal point along said at least one write bit line to a read bit line signal point along said at least one read bit line for output to a data output;

selectively passing said output signal to said at least one write bit line; and

selectively passing said write signal from said write bit line signal point along said at least one write bit line to said read bit line signal point along said at least one read bit line for output to said data output.

2. The method of claim 1, wherein said sense amplifier has an input, said write-read bypass device is operatively coupled to said sense amplifier input, and said write-read bypass device is configured to selectively pass said write signal from said write bit line signal point to said input of said sense amplifier, further comprising selectively passing said write signal from said write bit line signal point to said input of said sense amplifier.

3. A method comprising the steps of:

providing a dynamic random access memory circuit comprising;

at least one write bit line;

at least one read bit line;

a capacitive storage device;

a write access device, said write access device being operatively coupled to said capacitive storage device and said at least one write bit line;

a first sense amplifier, said first sense amplifier being operatively coupled to said at least one read bit line and configured to generate an output signal;

a refresh sense amplifier, said refresh sense amplifier being operatively coupled to said at least one write bit line and configured to generate a refresh sense amplifier output signal; and

a refresh bypass device, said refresh bypass device being operatively associated with said refresh sense amplifier and said at least one write bit line so as to selectively pass said refresh sense amplifier output signal to said at least one write bit line;

generating said output signal with said first sense amplifier;

generating said refresh sense amplifier output signal with said refresh sense amplifier; and

selectively passing said refresh sense amplifier output signal to said at least one write bit line, with said refresh bypass device.

4. The method of claim 3, wherein, in said providing step, said refresh bypass device is separate from and operatively coupled to said refresh sense amplifier.

5. The method of claim 3, wherein, in said providing step, said refresh bypass device is implemented inside said refresh sense amplifier.

6. The method of claim 3, wherein, in said providing step, said dynamic random access memory circuit further comprises a write-read bypass device, said write-read bypass device being coupled to said at least one write bit line and said at least one read bit line and being configured to selectively pass a write signal from a write bit line signal point along said at least one write bit line to a read bit line signal point along said at least one read bit line for output to a data output;

further comprising selectively passing said write signal from said write bit line signal point along said at least one write bit line to said read bit line signal point along said at least one read bit line for output to said data output.

7. The method of claim 6, wherein, in said providing step, said first sense amplifier has an input, said write-read bypass device is operatively coupled to said first sense amplifier input, and said write-read bypass device is configured to selectively pass said write signal from said write bit line signal point to said input of said sense amplifier;

further comprising selectively passing said write signal from said write bit line signal point to said input of said sense amplifier.

8. The method of claim 7, wherein, in said providing step, said dynamic random access memory circuit further comprises a refresh read bypass device, said refresh read bypass device being operatively coupled to said refresh sense amplifier and at least one of said read bit line and said first sense amplifier, said refresh sense amplifier being configured to selectively pass said refresh sense amplifier output signal to a signal point associated with one of said read bit line and said first sense amplifier for output to a data output;

further comprising selectively passing said refresh sense amplifier output signal to said signal point associated with said one of said read bit line and said first sense amplifier for output to said data output.

9. The method of claim 8, wherein, in said providing step, said first sense amplifier has an input, said refresh read bypass device is operatively coupled to said first sense amplifier input, and said refresh read bypass device is configured to selectively pass said refresh sense amplifier output signal to said input of said first sense amplifier;

further comprising selectively passing said refresh sense amplifier output signal to said input of said first sense amplifier.

10. The method of claim 9, wherein, in said providing step, said first sense amplifier has a tristate output, said refresh read bypass device is operatively coupled to said first sense amplifier tristate output, and said refresh read bypass device is configured to selectively pass said refresh sense amplifier output signal to said tristate output of said first sense amplifier;

further comprising selectively passing said refresh sense amplifier output signal to said tristate output of said first sense amplifier

11. A method for refreshing data to a dynamic random access memory circuit, comprising the steps of:

reading said data from a capacitive storage device of a memory cell of said circuit into a refresh sense amplifier, wherein said data is read from said capacitive storage device via an exclusive write port of said cell; and

writing said data from said sense amplifier to said capacitive storage device.

12. The method of claim 11, wherein said writing of said data from said sense amplifier to said capacitive storage device is performed via a refresh bypass device.