Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands
First Claim
1. An integrated circuit memory device comprising:
- a memory cell array;
a mode register configured to store information defining an operational characteristic of the memory device;
a command decoder configured to accept a selective mode register set command responsive to an enable signal received on a predetermined pin of the integrated circuit memory device and to reject a selective mode register set command responsive to a disable signal received on the predetermined pin of the integrated circuit memory device during a selective mode register set operation, so that information of the selective mode register set command is saved to the mode register when the enable signal is received on the predetermined pin during the selective mode register set operation; and
a data input/output buffer configured to control writing of data to the memory cell array during a write operation and/or reading of data from the memory cell array during a read operation in accordance with the operational characteristic defined by the information saved in the mode register.
0 Assignments
0 Petitions
Accused Products
Abstract
A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed.
-
Citations
9 Claims
-
1. An integrated circuit memory device comprising:
-
a memory cell array; a mode register configured to store information defining an operational characteristic of the memory device; a command decoder configured to accept a selective mode register set command responsive to an enable signal received on a predetermined pin of the integrated circuit memory device and to reject a selective mode register set command responsive to a disable signal received on the predetermined pin of the integrated circuit memory device during a selective mode register set operation, so that information of the selective mode register set command is saved to the mode register when the enable signal is received on the predetermined pin during the selective mode register set operation; and a data input/output buffer configured to control writing of data to the memory cell array during a write operation and/or reading of data from the memory cell array during a read operation in accordance with the operational characteristic defined by the information saved in the mode register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An integrated circuit memory device comprising:
-
a memory cell array; a plurality of data input/output pins configured to receive data from a memory controller to be written to the memory cell array during a data write operation, the data input/output pins being further configured to provide data to the memory controller from the memory cell array during a data read operation; and a mode register configured to store information defining an operational characteristic of the memory device, wherein the mode register is configured to be set using the data input/output bus.
-
Specification