Sensing scheme for the semiconductor memory

• US 20090059686A1
• Filed: 09/04/2007
• Published: 03/05/2009
• Est. Priority Date: 09/04/2007
• Status: Abandoned Application

• Current Assignee: Taiwan Imaging Tek Corporation
• Original Assignee: Taiwan Imaging Tek Corporation
• Inventors: Sung, Chih-Ta Star
• Application Number:
  US11/897,947
• Publication Number:
  US 20090059686A1
• Time in Patent Office: Days
• US Class Current: 365/189.110
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to turn off the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation.

Claims

1. A semiconductor memory sensing scheme in a memory array, comprising:

a memory array with memory cells, that generates a first voltage output and a second voltage output when the memory cell is accessed, wherein the first voltage output ramps from a predetermined voltage level to a higher voltage level, and the second voltage output keeps in a predetermined voltage level;

a first N-type device coupled between ground and one corresponding bit line of the memory array, wherein discharging the bit line voltage when memory array accessing is completed;

a second N-type device coupled between ground and one corresponding bit line-bar of the memory array, wherein discharging the bit line voltage when memory array accessing is completed; and

a differential amplifier with two input nodes coupled to the bit line and the bit line-bar of the memory array to generate a first sense output voltage if the first voltage output of one memory cell is higher than a second voltage output of the one memory cell and to generate a second sense output voltage if the first voltage output of one memory cell is lower than a second voltage output of the one memory cell.

2. The circuit as recited in claim 1, wherein the memory cell has a static random access memory (SRAM) device comprising of six semiconductor MOS devices.

3. The circuit as recited in claim 1, wherein the memory cell has a pair of P-type MOS devices as the pass devices with gate connecting to the world line and are turned ON and starts charging the bit line and bit line-bar when the word line is selected.

4. The circuit as recited in claim 2, wherein the SRAM cell has at least one back-to-back inverting circuit with both inverting devices hooked up to VDD through a pull-up device and to Ground through a pull-down device.

5. The circuit as recited in claim 4, wherein the pull-up device has a P-type semiconductor device and the pull-down device has an N-type semiconductor device.

6. The circuit as recited in claim 4, wherein the pull-up device has a resistor and the pull-down device has another resistor.

7. The circuit as recited in claim 1, wherein the differential amplifier has an amplifier circuit with at least two differential input nodes and a control input for enabling and disabling the amplifier circuit.

8. A control circuit for a semiconductor memory array, comprising:

a sense amplifier for amplifying output from a memory cell; and

a self-timer coupled to the sense amplifier for counting a time and sending out control signals to shut off the sense amplifier according to the time and pulling down a word line to avoid further current sinking through the memory cell; and

a delay device for controlling a second time to discharge a bit line and a bit line-bar of the memory array.

9. The circuit as recited in claim 8, further comprising a delay device for controlling a second time to discharge a bit line and a bit line-bar of the memory array.

10. The circuit as recited in claim 8, wherein the self-timer counts the time of differentiating a voltage between the bit line and the bit line-bar.

11. The circuit as recited in claim 8, wherein when the differential voltage of the bit line and the bit line-bar reaches a predetermined threshold, the self-timer sends a signal to turn off the word line.

12. The circuit as recited in claim 8, wherein when the differential voltage of the bit line and the bit line-bar reaches a predetermined threshold, the self-timer sends a signal to enable the sense amplifier.

13. The circuit as recited in claim 9, wherein when the differential voltage of the bit line and the bit line-bar reaches a predetermined threshold, the delay device send a signal to discharge the bit line and bit line-bar.

14. The circuit as recited in claim 9, wherein the delay device postpones the time and sends a signal to turn on N-type devices to discharge the bit line and bit line-bar to avoid overlapping of the word line and the bit line and bit line-bar.