NONPLANAR SEMICONDUCTOR DEVICE WITH PARTIALLY OR FULLY WRAPPED AROUND GATE ELECTRODE AND METHODS OF FABRICATION

• US 20090061572A1
• Filed: 10/28/2008
• Published: 03/05/2009
• Est. Priority Date: 06/27/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doyle, Brian S., Rios, Rafael, Hareland, Scott A., Datta, Suman, Linton, Tom
• Granted Patent: US 7,820,513 B2
• Time in Patent Office: Days
• US Class Current: 438/157
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a nonplanar semiconductor device comprising:

forming a semiconductor body having a top surface opposite a bottom surface and a pair of laterally opposite sidewalls above an insulating substrate;

forming a gate dielectric on said top surface of said semiconductor body, on said laterally opposite sidewalls of said semiconductor body, and on at least a portion of said bottom surface of said semiconductor body;

forming a gate electrode on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body and subadjacent to said gate dielectric formed on at least a portion of said bottom surface of said semiconductor body; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

2. The method for forming said semiconductor device of claim 1 wherein said gate dielectric and gate electrode are formed beneath the entire channel region of said semiconductor body.

3. The method of claim 1 wherein a portion of the bottom surface of said semiconductor body is formed on said insulating substrate wherein said portion on said insulating substrate is located beneath said gate electrode above said top surface of said semiconductor body.

4. The method of claim 1 wherein said semiconductor body is a single crystalline silicon film.

5. The method of claim 1 wherein said semiconductor body is selected from the group consisting of germanium, silicon germanium, gallium arsenide, InSb, GaP, GaSb and carbon nanotubes.

6. The method of claim 1 wherein said gate electrode comprises a material selected from the group consisting of polycrystalline silicon, tungsten, tantalum, titanium and metal nitrides.

7. The method of claim 1 wherein said insulating substrate comprises an oxide film formed on a monocrystalline silicon substrate.

8. The method of claim 1 further including forming at least one additional semiconductor body having a top surface and a bottom surface, and a pair of laterally opposite sidewalls and forming a gate dielectric layer over said top surface, said bottom surface and said sidewalls of said at least one other semiconductor body, and wherein said gate electrode is formed on said gate dielectric on said top surface of said at least one other semiconductor body, and adjacent to said gate dielectric on said laterally opposite sidewalls of said at least one other semiconductor body, and beneath the gate dielectric on said bottom surface of said at least one other semiconductor body.

9. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a pair of laterally opposite sidewalls and a top surface and a bottom surface on an insulating substrate;

removing a portion of said insulating substrate from beneath said semiconductor body to undercut said semiconductor body and expose a portion of said bottom surface of said semiconductor body;

forming a gate dielectric on said top surface of said semiconductor body, on said sidewalls of said semiconductor body, and on said exposed bottom portion of said semiconductor body;

depositing a gate material over and around said semiconductor body and beneath said exposed portion of said semiconductor body;

etching gate electrode material into a gate electrode utilizing a first anisotropic etch followed by a isotropic etch to form a gate electrode which is formed over the gate dielectric layer on the top surface of said semiconductor body and is formed adjacent the gate dielectric formed on the sidewalls of said semiconductor body and is formed beneath said gate dielectric formed on said exposed portions of said bottom surface of said semiconductor body; and

placing dopants into said semiconductor body on opposite sides of said gate electrode to form a pair of source/drain regions.

10. The method of claim 9 wherein said semiconductor body is formed from single crystalline silicon.

11. The method of claim 10 wherein said insulating substrate comprises a lower monocrystalline silicon substrate and a top silicon oxide,

12. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface and a bottom surface and a pair of laterally opposite sidewalls on an insulating substrate;

forming a dielectric film over and around said semiconductor body, wherein said dielectric film has an opening which exposes the channel region of said semiconductor body;

removing a portion of said insulating substrate in said opening beneath said semiconductor body to expose at least a portion of said bottom surface of said semiconductor body;

forming a gate dielectric layer on said top surface and said sidewalls of said semiconductor body in said opening and on said exposed portion of said bottom surface of said semiconductor body;

blanket depositing a gate electrode material over said dielectric film and into said opening and on said gate dielectric layer on said top surface of said semiconductor body, adjacent to said gate dielectric on said sidewalls of said semiconductor body and beneath said gate dielectric on said exposed portions of said semiconductor body;

removing said gate electrode material from the top surface of said dielectric film to form a gate electrode;

removing said dielectric film; and

placing dopants into said semiconductor body on opposite sides of said electrode to form a pair source/drain regions.

13. The method of claim 12 wherein said semiconductor body is formed from single crystalline silicon.

14. The method of claim 13 wherein said insulating substrate comprises a lower monocrystalline silicon substrate and a top silicon oxide insulating film.

15. A method of forming a nonplanar transistor comprising:

forming a semiconductor body having a top surface and bottom surface and a pair of laterally opposite sidewalls on an insulating substrate;

forming a sacrificial gate electrode above said top surface of said semiconductor body and adjacent to said laterally opposite sidewalls of said semiconductor body, said sacrificial gate electrode having a pair of laterally opposite sidewalls;

placing dopants into said semiconductor body on opposite sides of said sacrificial gate electrode to form a pair of source/drain extensions on opposite sides of said gate electrode;

forming a pair of sidewall spacers along laterally opposite sidewalls of said sacrificial gate electrode;

forming silicon on said semiconductor body adjacent to said sidewall spacers;

placing dopants into said silicon and into said semiconductor body in alignment with said sidewall spacers;

forming a silicide on said silicon formed on said semiconductor body adjacent to said sidewall spacers;

forming a dielectric layer over said silicide, said sacrificial gate electrode and said sidewall spacers;

planarizing said dielectric layer until the top surface of said dielectric layer is planar with the top surface of said sacrificial gate electrode and said sacrificial gate electrode is exposed;

removing said sacrificial gate electrode to expose the channel region of said semiconductor body and said insulating substrate;

removing a portion of said insulating substrate in said opening beneath said semiconductor body to expose at least a portion of said bottom surface of said semiconductor body;

forming a gate dielectric layer on said top surface and said sidewalls of said semiconductor body in said opening and on said portion of said exposed bottom surface of said semiconductor body;

blanket depositing a gate electrode material on said gate dielectric layer and into said opening and on said gate dielectric layer on said top surface of said semiconductor body, adjacent to said gate dielectric on said sidewalls of said semiconductor body, and beneath said gate dielectric on said exposed portion of said bottom surface of said semiconductor body; and

removing said gate electrode material from the top surface of said dielectric film to form a gate electrode.

16. The method of claim 15 wherein semiconductor body is formed from single crystalline silicon.

17. The method of claim 16 wherein said insulating substrate comprises a lower monocrystalline silicon substrate and a top silicon insulating film.