SELF-REFERENCING COMMUNICATION IN IMPLANTABLE DEVICES

• US 20090062879A1
• Filed: 08/29/2008
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Original Assignee: Proteus Digital Health, Inc. (Otsuka Holdings Company Limited)
• Inventors: Arne, Lawrence, Bi, Yafei, Li, Haifeng, Zdeblick, Mark, Withrington, Jonathan, Jani, Nilay
• Granted Patent: US 8,187,161 B2
• Time in Patent Office: Days
• US Class Current: 607/32
• CPC Class Codes: A61N 1/025 Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors
• CPC Class Codes: A61N 1/37288 Communication to several implantable medical devices within one patient

Abstract

Various aspects of the present invention enable robust, reliable control functionality for effectors present on intraluminal, e.g., vascular leads, as well as other types of implantable devices. Aspects of the invention include implantable integrated circuits that have self-referencing and self-clocking signal encoding, and are capable of bidirectional communication. Also provided by the invention are effector assemblies that include the integrated circuits, as well as implantable medical devices, e.g., pulse generators that include the same, as well as systems and kits thereof and methods of using the same, e.g., in pacing applications, including cardiac resynchronization therapy (CRT) applications.

Claims

1. An implantable system, comprising:

(a) a controller having an amplifier configured to amplify a voltage difference across a variable resistor, said variable resistor being coupled to a first supply voltage and a first lead line, said controller being coupled to said first and a second lead line; and

(b) a plurality of implantable integrated circuits coupled to said first and second lead lines, wherein a selected one of said implantable integrated circuits is configured to reduce an impedance across said first and second lead lines to change said voltage difference for communication of an electrode configuration to said controller.

2. The implantable system of claim 2, further comprising detection logic coupled to an output of said amplifier, said detection logic being configured to derive said electrode configuration.

3. The implantable system of claim 2, wherein said variable resistor is changed to about 300Ω

for said amplification of said voltage difference.

4. The implantable system of claim 2, further comprising a second resistor coupled to said second lead line and a second supply voltage.

5. The implantable system of claim 2, wherein said impedance across said first and second lead lines is reduced using a transistor, said transistor being enabled during a predetermined mode.

6. The implantable system of claim 2, wherein said impedance across said first and second lead lines is reduced using first and second transistors, said first transistor being enabled during a predetermined mode, said second transistor being enabled for a predetermined duration when entering the predetermined mode.

7. A method for communicating an electrode configuration of an implantable device, the method comprising:

(a) receiving a command from a controller;

(b) receiving an address from the controller, said address corresponding to one of a plurality of implantable devices coupled to said controller; and

(c) sending a bit string to said controller in response to said command when said address matches a predetermined address of said implantable device, wherein said bit string is configured to convey said electrode configuration.

8. The method of claim 7, wherein each bit of said bit string comprises a signal having first and second high phases and first and second low phases.

9. The method of claim 8, wherein an amplitude of said first low phase relative to an amplitude of said second low phase determines a state of said bit.

10. The method of claim 7, wherein said command comprises a sequence of two encoded symbols.

11. The method of claim 7, wherein said address comprises a sequence of two encoded symbols.

12. A computer-readable storage device, comprising:

(a) one or more instructions for receiving a command from a controller;

(b) one or more instructions for receiving an address from the controller, said address corresponding to one of a plurality of implantable devices coupled to said controller; and

(c) one or more instructions for sending a bit string to said controller in response to said command when said address matches a predetermined address of said implantable device, wherein said bit string is configured to convey said electrode configuration.

13. The computer-readable storage device of claim 12, wherein each bit of said bit string comprises a signal having first and second high phases and first and second low phases.

14. The computer-readable storage device of claim 13, wherein an amplitude of said first low phase relative to an amplitude of said second low phase determines a state of said bit.

15. The computer-readable storage device of claim 12, wherein said command comprises a sequence of two encoded symbols.

16. The computer-readable storage device of claim 12, wherein said address comprises a sequence of two encoded symbols.

17. An implantable controller having an interface configured to communicate with an implantable satellite device, said interface comprising:

(a) a ground terminal; and

(b) a signal terminal configured to transmit a series of encoded signals to said implantable satellite device, and to receive an electrode configuration of said implantable satellite device in response to said series of encoded signals.

18. The implantable controller of claim 17, wherein said electrode configuration comprises an enable state and a polarity state for each electrode associated with said implantable satellite device.

19. The implantable controller of claim 17, wherein said series of encoded signals comprises two symbols for a command followed by two symbols for an address.

20. The implantable controller of claim 17, wherein said encoded signal comprises about a 500 mV variation over a nominal 5 V signal.

21. The implantable controller of claim 20, wherein said electrode configuration comprises a bit string having an additional variation of about 100 mV from said 500 mV variation.

22. A method of determining an unresponsive implantable satellite device, the method comprising:

(a) sampling and holding a first data bit to provide a first channel signal;

(b) sampling and holding a second data bit to provide a second channel signal;

(c) comparing said first and second channel signals;

(d) and

generating an error bit and return data in response to said comparison of said first and second channel signals for said unresponsive satellite device determination.