SELF-REFERENCING COMMUNICATION IN IMPLANTABLE DEVICES
First Claim
1. An implantable integrated circuit, comprising:
- (a) a first capacitor configured to be charged when a first phase control signal is asserted, said first phase control signal being related to a first predetermined phase of an encoded signal;
(b) a second capacitor configured to be charged when a second phase control signal is asserted, said second phase control signal being related to a second predetermined phase of said encoded signal; and
(c) a first comparator coupled to said first and second capacitors, said first comparator being configured to provide a first comparison result that indicates which of said first and second predetermined phases has a longer duration.
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Accused Products
Abstract
Various aspects of the present invention enable robust, reliable control functionality for effectors present on intraluminal, e.g., vascular leads, as well as other types of implantable devices. Aspects of the invention include implantable integrated circuits that have self-referencing and self-clocking signal encoding, and are capable of bidirectional communication. Also provided by the invention are effector assemblies that include the integrated circuits, as well as implantable medical devices, e.g., pulse generators that include the same, as well as systems and kits thereof and methods of using the same, e.g., in pacing applications, including cardiac resynchronization therapy (CRT) applications.
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Citations
22 Claims
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1. An implantable integrated circuit, comprising:
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(a) a first capacitor configured to be charged when a first phase control signal is asserted, said first phase control signal being related to a first predetermined phase of an encoded signal; (b) a second capacitor configured to be charged when a second phase control signal is asserted, said second phase control signal being related to a second predetermined phase of said encoded signal; and (c) a first comparator coupled to said first and second capacitors, said first comparator being configured to provide a first comparison result that indicates which of said first and second predetermined phases has a longer duration. - View Dependent Claims (2, 3, 4, 5)
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6. A method for clock and data recovery in an implantable device, the method comprising:
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(a) recovering a first clock from first and second high phases of an encoded signal, and a second clock from first and second low phases of said encoded signal; (b) deriving first, second, third, and fourth phase control signals from said first and second recovered clocks; (c) comparing pulse durations of said first and second phase control signal to generate a first comparison result, and comparing pulse durations of said third and fourth phase control signals to generate a second comparison result; and (d) determining one of four symbols corresponding to said encoded signal using said first and second comparison results. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A computer-readable storage device, comprising:
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(a) one or more instructions for recovering a first clock from first and second high phases of an encoded signal, and a second clock from first and second low phases of said encoded signal; (b) one or more instructions for deriving first, second, third, and fourth phase control signals from said first and second recovered clocks; (c) one or more instructions for comparing pulse durations of said first and second phase control signal to generate a first comparison result, and comparing pulse durations of said third and fourth phase control signals to generate a second comparison result; and (d) one or more instructions for determining one of four symbols corresponding to said encoded signal using said first and second comparison results. - View Dependent Claims (13, 14, 15, 16, 17)
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18. An implantable controller having an interface configured to communicate to an implantable satellite device, said interface comprising:
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(a) a ground terminal; and (b) a signal terminal configured to transmit an encoded signal to said implantable satellite device, wherein said encoded signal comprises first and second high phases and first and second low phases. - View Dependent Claims (19, 20, 21, 22)
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Specification