PMU TESTING VIA A PE STAGE

• US 20090063085A1
• Filed: 09/05/2007
• Published: 03/05/2009
• Est. Priority Date: 09/05/2007
• Status: Abandoned Application

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Parks, Allan Joseph, Conner, George W.
• Application Number:
  US11/850,492
• Publication Number:
  US 20090063085A1
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

An apparatus for use in testing a device includes a parametric measurement unit to measure a first signal from the device, and pin electronics to provide a second signal to the device. The pin electronics includes circuitry along a path to the device. The parametric measurement unit is electrically connected to the device via the circuitry to receive the first signal via the circuitry.

Claims

1. An apparatus for use in testing a device, comprising:

a parametric measurement unit to measure a first signal from the device; and

pin electronics to provide a second signal to the device, the pin electronics comprising circuitry along a path to the device;

wherein the parametric measurement unit is configured to send a third signal to the pin electronics, the third signal being used to generate the second signal;

wherein the parametric measurement unit is electrically connected to the device via the circuitry to receive the first signal via the circuitry.

2. The apparatus of claim 1, wherein the circuitry further comprises an impedance circuit at least one transistor on each side of the impedance circuit.

3. The apparatus of claim 2, wherein each transistor comprises a first terminal that is electrically connected to the path to the device, a second terminal that is electrically connected along a path to the parametric measurement unit, and a third terminal that is electrically connected to a controlling device configured to provide a control signal;

and

wherein each transistor is configured to receive a control signal and to promote an electrical connection between the first terminal and the second terminal in response to the control signal.

4. The apparatus of claim 3, wherein the transistors comprise field effect transistors, the first terminal comprises a source, the second terminal comprises a drain, and the third terminal comprises a gate.

5. The apparatus of claim 3, wherein the transistors comprise bipolar junction transistors, the first terminal comprises a collector, the second terminal comprises an emitter, and the third terminal comprises a base.

6. The apparatus of claim 3, wherein the controlling device comprises a processing device configured to generate control signals for the transistor.

7. The apparatus of claim 2, wherein the impedance circuit comprises one or more resistors in a configuration that provides a resistance along the path.

8. The apparatus of claim 1, wherein the circuitry comprises:

a first signal line to the device;

a first transistor electrically connected between the first signal line and the parametric measurement unit;

a second signal line to the device; and

a second transistor electrically connected between the second signal line and the parametric measurement unit.

9. The apparatus of claim 8, further comprising:

a driver electrically connected to the second signal line between the second transistor and the device, the driver for pulling-down current from the second signal line.

10. A system for testing an electronic device, comprising:

a device interface board to hold the electronic device;

a testing device to send test signals to the electronic device and to receive response signals from the electronic device, the response signals resulting from at least some of the test signals; and

a processing device to provide control signals to the testing device, the control signals to affect operation of the testing device;

wherein the testing device comprises;

a pin electronics circuit to provide test signals to the device, the pin electronics circuit comprising at least two transistors; and

a parametric measurement unit to test the electronic device via the pin electronics circuit and to send a DC signal to the pin electronics circuit;

wherein the at least two transistors are configured to generate an AC signal from the DC signal.

11. The system of claim 10, wherein the parametric measurement unit is configured for use in measuring a voltage associated with the device in response to a current forced to the device via the pin electronics circuit.

12. The system of claim 10, wherein the parametric measurement unit is configured for use in determining a current associated with the device in response to a voltage forced to the device via the pin electronics circuit.

13. The system of claim 10, wherein the pin electronics circuit comprises differential signal lines to the device;

and

wherein the parametric measurement unit is configured for use in detecting a resistance between the differential signal lines via the pin electronics circuit.

14. The system of claim 13, further comprising:

a driver to draw current from a first differential signal line, through the device, to a second differential signal line.

15. The system of claim 14, wherein the pin electronics circuit comprises a signal line to the device;

and

wherein the parametric measurement unit is configured to determine a voltage on the signal line in response to a voltage forced onto the signal line by the pin electronics circuit.

16. The system of claim 10, wherein the test signals comprise AC test signals having a frequency of one gigahertz (1 GHz) or more.

17. A testing apparatus comprising:

a first circuit for providing AC test signals to a device, the first circuit comprising at least two transistors;

a second circuit for providing DC test signals to the device and for providing a voltage signal to the first circuit; and

circuitry for electrically connecting the first circuit to the second circuit;

wherein the second circuit is configured to measure electrical characteristics of the device via the circuitry and the first circuit; and

wherein the at least two transistors are configured to generate the AC test signal from the voltage signal.

18. The testing apparatus of claim 17, wherein the electrical characteristics comprise at least one of a voltage at the device and current from the device.

19. The testing apparatus of claim 17, wherein the first circuit comprises one or more signal lines for providing the AC test signals to the device;

and

wherein the circuitry comprises signal lines to electrically connect, to the second circuit, the one or more signal lines of the first circuit.

20. The testing apparatus of claim 17, further comprising one or more processing devices for controlling the first circuit to enable measurement of the electrical characteristics by the second circuit.

21. The testing apparatus of claim 17, wherein the AC test signals have a frequency of one gigahertz (1 GHz) or more.

22. The testing apparatus of claim 17, wherein the AC test signals have a frequency of two gigahertz (2 GHz) or more.