System and Method for Direct/Indirect Transmission of Information Using a Multi-Tiered Full-Graph Interconnect Architecture

• US 20090063728A1
• Filed: 08/27/2007
• Published: 03/05/2009
• Est. Priority Date: 08/27/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Rajamony, Ramakrishnan, Arimilli, Lakshminarayana B.
• Granted Patent: US 7,822,889 B2
• Time in Patent Office: Days
• US Class Current: 710/31
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A method, computer program product, and system are provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.

Claims

1. A method, in a data processing system, for transmitting data in a data network, the method comprising:

receiving, in a first processor of the data network, data to be transmitted to a second processor within the data network;

determining if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data;

selecting a communication link over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link; and

transmitting the data from the first processor to the second processor using the selected communication link.

2. The method of claim 1, wherein selecting the communication link over which to transmit the data comprises:

determining whether to transmit the data over a direct communication link to the final destination processor, wherein the final destination processor is the second processor, or to transmit the data over an indirect communication link to a second processor that is not the final destination processor, based on results of determining if the data has previously been routed through an indirect communication link.

3. The method of claim 1, wherein determining whether to transmit the data over the direct communication link or to transmit the data over the indirect communication link is based on a set of virtual channels in the data network.

4. The method of claim 3, wherein the set of virtual channels is determined by a switch that allocates one virtual channel for every hop of the longest indirect communication link in the data network.

5. The method of claim 3, wherein a subset of virtual channels within the set of virtual channels is associated with each processor within a plurality of processors within the data network.

6. The method of claim 5, wherein each virtual channel in the subset of virtual channels is at a different level and wherein each level is used by each processor based on the position of the processor within the selected communication link.

7. The method of claim 1, wherein the data network is a multi-tiered full-graph (MTFG) interconnect architecture data network comprising a plurality of processors, subsets of the plurality of processors comprising processor books in which processors of a processor book are coupled to one another, a plurality of processor books being coupled to one another to constitute a supernode, and wherein the first processor is in a first supernode and the second processor is in a second supernode.

8. A computer program product, for transmitting data in a data network, comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed in a first processor of the data network, causes the first processor to:

receive data to be transmitted to a second processor within the data network;

determine if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data;

select a communication link over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link; and

transmit the data from the first processor to the second processor using the selected communication link.

9. The computer program product of claim 8, wherein the computer readable program that causes the data processing system to select the communication link over which to transmit the data further causes the data processing system to:

determine whether to transmit the data over a direct communication link to the final destination processor, wherein the final destination processor is the second processor, or to transmit the data over an indirect communication link to the second processor that is not the final destination processor, based on results of determining if the data has previously been routed through an indirect communication link.

10. The computer program product of claim 8, wherein determining whether to transmit the data over the direct communication link or to transmit the data over the indirect communication link is based on a set of virtual channels in the data network.

11. The computer program product of claim 10, wherein the set of virtual channels is determined by a switch that allocates one virtual channel for every hop of the longest indirect communication link in the data network.

12. The computer program product of claim 10, wherein a subset of virtual channels within the set of virtual channels is associated with each processor within a plurality of processors within the data network.

13. The computer program product of claim 12, wherein each virtual channel in the subset of virtual channels is at a different level and wherein each level is used by each processor based on the position of the processor within the selected communication link.

14. The computer program product of claim 8, wherein the data network is a multi-tiered full-graph (MTFG) interconnect architecture data network comprising a plurality of processors, subsets of the plurality of processors comprising processor books in which processors of a processor book are coupled to one another, a plurality of processor books being coupled to one another to constitute a supernode, and wherein the first processor is in a first supernode and the second processor is in a second supernode.

15. A system for transmitting data in a data network, comprising:

a first processor in the data network; and

a memory coupled to the first processor, wherein the memory comprises instructions which, when executed by the first processor, cause the first processor to;

receive data to be transmitted to a second processor within the data network;

determine if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data;

select a communication link over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link; and

transmit the data from the first processor to the second processor using the selected communication link.

16. The system of claim 15, wherein the instructions to select the communication link over which to transmit the data comprises further instructions that cause each processor to:

determine whether to transmit the data over a direct communication link to the final destination processor, wherein the final destination processor is the second processor, or to transmit the data over an indirect communication link to a second processor that is not the final destination processor, based on results of determining if the data has previously been routed through an indirect communication link.

17. The system of claim 15, wherein determining whether to transmit the data over the direct communication link or to transmit the data over the indirect communication link is based on a set of virtual channels in the data network.

18. The system of claim 17, wherein the set of virtual channels is determined by a switch that allocates one virtual channel for every hop of the longest indirect communication link in the data network.

19. The system of claim 17, wherein a subset of virtual channels within the set of virtual channels is associated with each processor within a plurality of processors within the data network, wherein each virtual channel in the subset of virtual channels is at a different level, and wherein each level is used by each processor based on the position of the processor within the selected communication link.

20. The system of claim 15, wherein the data network is a multi-tiered full-graph (MTFG) interconnect architecture data network comprising a plurality of processors, subsets of the plurality of processors comprising processor books in which processors of a processor book are coupled to one another, a plurality of processor books being coupled to one another to constitute a supernode, and wherein the first processor is in a first supernode and the second processor is in a second supernode.