System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel

• US 20090063729A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 7,861,014 B2
• Time in Patent Office: Days
• US Class Current: 710/35
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0879 Burst mode
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.

Claims

1. A memory system, comprising:

a memory hub device integrated in a memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

burst logic integrated in the memory hub device, wherein the burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of read data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of read data on a memory channel, wherein the amount of read data is equal to or less than a conventional data burst amount of data for the set of memory devices.

2. The memory system of claim 1, wherein the memory hub device further comprises:

a memory device data interface coupled to the memory hub controller and the set of memory devices, wherein the memory hub controller controls the amount of read data that is transmitted using the burst length field by sending one or more control signals to the memory device data interface to thereby control an amount of data output by the memory device data interface.

3. The memory system of claim 2, wherein the memory hub device further comprises:

a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

4. The memory system of claim 3, wherein the memory hub device further comprises:

a multiplexer coupled to the link interface and the memory device data interface; and

a read data queue coupled to the multiplexer and the memory device data interface, wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface by sending one or more control signals to the multiplexer to select either a direct input from the memory device data interface or an input from the read data queue for output by the multiplexer to the link interface.

5. The memory system of claim 4, wherein the memory hub controller controls the output of data from the link interface to the external memory controller by providing a control signal specifying an amount of data provided to the link interface, and a start of the data.

6. The memory system of claim 4, wherein the memory hub controller sends a control signal to the multiplexer to select the input from the read data queue based on a state of the read data queue and a state of the link interface.

7. The memory system of claim 1, wherein the burst length field specifies one of a full burst amount of data, a half burst amount of data, or a quarter burst amount of data.

8. The memory system of claim 1, wherein a smallest amount of read data that may be specified in the burst length field is dependent upon an error correction code codeword.

9. The memory system of claim 1, wherein, in response to receiving a read access request, the memory hub controller forwards the read access request to the set of memory devices and, in response, receives a first portion of read data having an amount of data equal to the conventional data burst amount of data from the set of memory devices, and wherein the memory hub controller selects, based on the burst length field, a second portion of the read data having a smaller amount of data than the first portion of read data.

10. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

11. The memory system of claim 1, wherein the memory module is part of a data processing device.

12. The memory system of claim 1, wherein the memory module is part of a main memory of a data processing system.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, and wherein each memory module of the one or more memory modules comprise;

a memory hub device integrated in the memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

burst logic integrated in the memory hub device, wherein the burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of read data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of read data on a memory channel, wherein the amount of read data is equal to or less than a conventional data burst amount of data for the set of memory devices.

14. The data processing system of claim 13, wherein the memory hub device further comprises:

a memory device data interface coupled to the memory hub controller and the set of memory devices, wherein the memory hub controller controls the amount of read data that is transmitted using the burst length field by sending one or more control signals to the memory device data interface to thereby control an amount of data output by the memory device data interface.

15. The data processing system of claim 14, wherein the memory hub device further comprises:

a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

16. The data processing system of claim 15, wherein the memory hub device further comprises:

a multiplexer coupled to the link interface and the memory device data interface; and

a read data queue coupled to the multiplexer and the memory device data interface, wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface by sending one or more control signals to the multiplexer to select either a direct input from the memory device data interface or an input from the read data queue for output by the multiplexer to the link interface.

17. The data processing system of claim 16, wherein the memory hub controller controls the output of data from the link interface to the external memory controller by providing a control signal specifying an amount of data provided to the link interface, and a start of the data.

18. The data processing system of claim 16, wherein the memory hub controller sends a control signal to the multiplexer to select the input from the read data queue based on a state of the read data queue and a state of the link interface.

19. The data processing system of claim 13, wherein the burst length field specifies one of a full burst amount of data, a half burst amount of data, or a quarter burst amount of data.

20. The data processing system of claim 13, wherein a smallest amount of read data that may be specified in the burst length field is dependent upon an error correction code codeword.

21. The data processing system of claim 13, wherein, in response to receiving a read access request, the memory hub controller forwards the read access request to the set of memory devices and, in response, receives a first portion of read data having an amount of data equal to the conventional data burst amount of data from the set of memory devices, and wherein the memory hub controller selects, based on the burst length field, a second portion of the read data having a smaller amount of data than the first portion of read data.