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System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel

  • US 20090063730A1
  • Filed: 08/31/2007
  • Published: 03/05/2009
  • Est. Priority Date: 08/31/2007
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • a memory hub device integrated in a memory module; and

    a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

    burst logic integrated in the memory hub device, wherein the burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data; and

    a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of write data on a memory channel, wherein the amount of write data is equal to or less than a conventional data burst amount for the set of memory devices.

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