System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel

• US 20090063730A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 7,584,308 B2
• Time in Patent Office: Days
• US Class Current: 710/35
• CPC Class Codes: G06F 13/161 with latency improvement

Abstract

A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount.

Claims

1. A memory system, comprising:

a memory hub device integrated in a memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

burst logic integrated in the memory hub device, wherein the burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of write data on a memory channel, wherein the amount of write data is equal to or less than a conventional data burst amount for the set of memory devices.

2. The memory system of claim 1, wherein the memory hub device further comprises:

a memory device data interface coupled to the memory hub controller and the set of memory devices, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field by sending one or more control signals to the memory device data interface to thereby control an amount of data output by the memory device data interface.

3. The memory system of claim 2, wherein the memory hub controller controls the amount of write data that is transmitted by generating a data mask control signal based on the burst length field and transmits the data mask control signal to the memory device data interface at substantially a same time as data is input to the memory device data interface.

4. The memory system of claim 3, wherein the data mask control signal causes the memory device data interface to transmit, as valid write data, only a portion of the data input to the memory device data interface corresponding to the amount of write data determined by the burst logic.

5. The memory system of claim 2, wherein the memory hub device further comprises:

a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

6. The memory system of claim 5, wherein the memory hub device further comprises:

a multiplexer coupled to the link interface and the memory device data interface; and

a write data queue coupled to the multiplexer and the memory device data interface, wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface by sending one or more control signals to the multiplexer to select either a direct input from the link interface or an input from the write data queue for output by the multiplexer to the memory device data interface.

7. The memory system of claim 1, wherein the burst length field specifies one of a full burst amount of data, a half burst amount of data, or a quarter burst amount of data.

8. The memory system of claim 1, wherein a smallest amount of write data that may be specified in the burst length field is dependent upon an error correction code codeword.

9. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

10. The memory system of claim 1, wherein the memory module is part of a data processing device.

11. The memory system of claim 1, wherein the memory module is part of a main memory of a data processing system.

12. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, and wherein each memory module of the one or more memory modules comprises;

a memory hub device integrated in the memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

burst logic integrated in the memory hub device, wherein the burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data; and

a memory hub controller integrated in the memory hub device, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field and wherein the memory hub device transmits the amount of write data on a memory channel, wherein the amount of write data is equal to or less than a conventional data burst amount for the set of memory devices.

13. The data processing system of claim 12, wherein the memory hub device further comprises:

a memory device data interface coupled to the memory hub controller and the set of memory devices, wherein the memory hub controller controls the amount of write data that is transmitted using the burst length field by sending one or more control signals to the memory device data interface to thereby control an amount of data output by the memory device data interface.

14. The data processing system of claim 13, wherein the memory hub controller controls the amount of write data that is transmitted by generating a data mask control signal based on the burst length field and transmits the data mask control signal to the memory device data interface at substantially a same time as data is input to the memory device data interface.

15. The data processing system of claim 14, wherein the data mask control signal causes the memory device data interface to transmit, as valid write data, only a portion of the data input to the memory device data interface corresponding to the amount of write data determined by the burst logic.

16. The data processing system of claim 13, wherein the memory hub device further comprises:

a link interface, coupled to the memory device data interface and the memory hub controller, that provides a communication path between the memory module and an external memory controller, and wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface.

17. The data processing system of claim 16, wherein the memory hub device further comprises:

a multiplexer coupled to the link interface and the memory device data interface; and

a write data queue coupled to the multiplexer and the memory device data interface, wherein the memory hub controller controls the transfer of data between the memory device data interface and the link interface by sending one or more control signals to the multiplexer to select either a direct input from the link interface or an input from the write data queue for output by the multiplexer to the memory device data interface.

18. The data processing system of claim 12, wherein the burst length field specifies one of a full burst amount of data, a half burst amount of data, or a quarter burst amount of data.

19. The data processing system of claim 12, wherein a smallest amount of write data that may be specified in the burst length field is dependent upon an error correction code codeword.

20. The data processing system of claim 12, wherein the one or more memory modules are one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).