Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel

• US 20090063731A1
• Filed: 09/05/2007
• Published: 03/05/2009
• Est. Priority Date: 09/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 7,558,887 B2
• Time in Patent Office: Days
• US Class Current: 710/35
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices.

Claims

1. A method for controlling an amount of data transmitted to or from a memory module, comprising:

responsive to an access request, determining, in a memory hub controller integrated in the memory module, the amount of data to be transmitted to or from a set of memory devices of the memory module,

generating, in the memory hub controller, a burst length field corresponding to the amount of data; and

controlling, by the memory hub controller, the amount of data that is transmitted to or from the memory devices using the burst length field, wherein the amount of data is equal to or less than a standard data burst amount of data for the set of memory devices.

2. The method of claim 1, wherein the data is read data that is transmitted from the set of memory devices to a memory controller external to the memory module.

3. The method of claim 1, wherein the data is write data that is transmitted to the set of memory devices from a memory controller external to the memory module.

4. The method of claim 1, wherein the determining and generating operations are performed by burst control logic provided in the memory hub controller.

5. The method of claim 1, wherein controlling the amount of data that is transmitted comprises sending one or more control signals from the memory hub controller to a memory device data interface of the memory module based on the burst length field to thereby control the amount of data output by the memory device data interface to or from the set of memory devices.

6. The method of claim 1, wherein controlling the amount of data that is transmitted comprises controlling a transfer of data between a memory device data interface that couples the memory hub device with the set of memory devices, and a link interface that couples the memory module with an external memory controller.

7. The method of claim 6, wherein controlling the transfer of data between the memory device data interface and the link interface comprises:

sending one or more control signals to a multiplexer coupled to the link interface and the memory device data interface, to select either a direct input from the memory device data interface or an input from a read data queue for output by the multiplexer to the link interface.

8. The method of claim 7, wherein controlling the amount of data that is transmitted further comprises controlling an output of data from the link interface to the external memory controller by providing a control signal from the memory hub controller specifying the amount of data provided to the link interface and a start of the data.

9. The method of claim 7, wherein the memory hub controller sends a control signal to the multiplexer to select the input from the read data queue based on a state of the read data queue and a state of the link interface.

10. The method of claim 1, wherein the burst length field specifies one of a full burst amount of data, a half burst amount of data, or a quarter burst amount of data.

11. The method of claim 2, wherein a smallest amount of the read data that may be specified in the burst length field is dependent upon an error correction code codeword.

12. The method of claim 1, wherein the access request is a read access request, and wherein controlling the amount of data that is transmitted comprises:

forwarding, by the memory hub controller, the read access request to the set of memory devices;

in response, receiving a first portion of read data having the amount of data equal to the standard data burst amount of data from the set of memory devices;

selecting, by the memory hub controller, based on the burst length field, a second portion of the read data having a smaller amount of data than the first portion of read data, for transmission to a memory controller external to the memory module.

13. The method of claim 6, wherein controlling the amount of data that is transmitted comprises:

controlling an amount of write data that is transmitted by a memory device data interface of a memory hub device of the memory module to the set of memory devices based on the burst length field by sending one or more control signals to the memory device data interface to thereby control the amount of data output by the memory device data interface to the set of memory devices.

14. The method of claim 13, wherein controlling the amount of data that is transmitted comprises:

generating a data mask control signal based on the burst length field; and

transmitting the data mask control signal to the memory device data interface at substantially a same time as data is input to the memory device data interface.

15. The method of claim 14, wherein the data mask control signal causes the memory device data interface to transmit, as valid write data, only a portion of the data input to the memory device data interface corresponding to the amount of write data specified by the burst length field.

16. The method of claim 13, wherein controlling the amount of data that is transmitted further comprises:

sending one or more control signals to a multiplexer coupled to the link interface and the memory device data interface, to select either a direct input from the link interface or an input from a write data queue for output by the multiplexer to the memory device data interface.

17. The method of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

18. The method of claim 1, wherein the memory module is part of a data processing device.

19. The method of claim 1, wherein the memory module is part of a main memory of a data processing system.