BUS CONTROLLER

• US 20090063734A1
• Filed: 02/27/2006
• Published: 03/05/2009
• Est. Priority Date: 03/14/2005
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Higaki, Nobuo, Kurata, Kazushi
• Application Number:
  US11/817,094
• Publication Number:
  US 20090063734A1
• Time in Patent Office: Days
• US Class Current: 710/52
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush.

Claims

1. A bus controller that controls a bus between a processor and a memory, said bus controller comprising:

a buffer unit operable to temporarily hold data to be stored from the processor into the memory, on a first-in first-out basis;

a reception unit operable to receive a trigger signal that causes said buffer unit to be partially flushed;

a pointer holding unit operable to hold a pointer which indicates end data held by said buffer unit at a time when the trigger signal is received;

a writing unit operable to write, in accordance with the trigger signal, a portion of the data held by said buffer unit into the memory so as to partially flush said buffer unit, the portion ranging from start data through data which is indicated by the pointer among the data held by said buffer unit; and

a wait generating unit operable to generate a wait signal for a specific access instruction to be executed by the processor, until said writing unit completes the partial flush.

2. The bus controller according to claim 1,

wherein said reception unit is operable to receive the trigger signal, the trigger signal being outputted from the processor when an instruction other than an instruction to access the memory is executed.

3. The bus controller according to claim 1,

wherein said reception unit is operable to receive the trigger signal, the trigger signal being outputted from the processor when the processor executes a store instruction having the partial flush.

4. The bus controller according to claim 1,

wherein the specific access instruction is an instruction to access a device which is different from the memory.

5. The bus controller according to claim 1,

wherein the specific access instruction is a load instruction.

6. The bus controller according to claim 1,

wherein said buffer unit includes:

a data buffer operable to temporarily hold data to be stored from the processor into the memory, on a first-in first-out basis;

an address buffer operable to hold an address corresponding to the data to be stored; and

a comparison unit operable to compare a load address outputted from the processor with an address held by said address buffer, and

said wait generating unit is operable to generate the wait signal when a comparison result from said comparison unit shows that the load address matches the address held by said address buffer.

7. The bus controller according to claim 6,

wherein said address buffer is operable to hold addresses respectively corresponding to the start data through the end data, the start data through the end data being held by said buffer unit when the trigger signal is received, and

said comparison unit is operable to compare, with the load address outputted from the processor, each of the addresses which respectively correspond to the start data through the end data held by said address buffer.

8. The bus controller according to claim 6,

wherein said address buffer is operable to hold addresses respectively corresponding to the start data through the end data, the start data through the end data being held by said buffer unit when the trigger signal is received, and

said comparison unit is operable to compare, with the load address outputted from the processor, each of the addresses which respectively correspond to the respective data that is not written into the memory among the data to be partially flushed, and operable not to compare, with the load address outputted from the processor, each of the addresses which respectively correspond to the respective data that has been written into the memory among the data to be partially flushed.

9. The bus controller according to claim 7,

wherein said comparison unit is further operable to compare a store address outputted from the processor with the address held by said address buffer,

when a comparison result from said comparison unit shows that the store address matches one of the addresses held by said address buffer, and the partial flush is completed, said wait generating unit is further operable to have writing of data, from a data memory into the memory, wait, the data corresponding to the matching address, and

when a subsequent comparison result from said comparison unit shows that the load address outputted from the processor matches one of the addresses held by said address buffer, said wait generating unit is operable to clear said address buffer.

10. The bus controller according to claim 7,

wherein said comparison unit is further operable to compare a store address outputted from the processor with the address held by said address buffer,

when a comparison result from said comparison unit shows that the store address matches one of the addresses held by said address buffer, and the partial flush is completed, said wait generating unit is further operable to have writing of data, from the data memory into the memory, wait, the data corresponding to the matching address, and

said wait generating unit is operable to clear said address buffer when the specific access instruction is completed.

11. The bus controller according to claim 1, further comprising:

a second buffer unit having the same configuration as said buffer unit which is referred to as a first buffer;

a designation unit operable to designate one of said first buffer unit and said second buffer unit as current; and

a switching unit operable to switch the current designation of said designation unit, in accordance with the trigger signal, and

wherein said writing unit and said wait generating unit have, as an object, one of said buffer units which is not designated as current, and

one of said buffer units which is designated as current is operable to hold data to be stored from the processor.

12. The bus controller according to claim 7, further comprising:

a second buffer unit having the same configuration as said buffer unit which is referred to as a first buffer;

a designation unit operable to designate one of said first buffer unit and said second buffer unit as current; and

a switching unit operable to switch the current designation of said designation unit, in accordance with the trigger signal, and

wherein said writing unit and said wait generating unit have, as an object, one of said buffer units which is not designated as current, and

one of said buffer units which is designated as current is operable to hold data to be stored from the processor.

13. The bus controller according to claim 8, further comprising:

a second buffer unit having the same configuration as said buffer unit which is referred to as a first buffer;

a designation unit operable to designate one of said first buffer unit and said second buffer unit as current; and

a switching unit operable to switch the current designation of said designation unit, in accordance with the trigger signal, and

wherein said writing unit and said wait generating unit have, as an object, one of said buffer units which is not designated as current, and

one of said buffer units which is designated as current is operable to hold data to be stored from the processor.

14. The bus controller according to claim 9, further comprising:

a second buffer unit having the same configuration as said buffer unit which is referred to as a first buffer;

a designation unit operable to designate one of said first buffer unit and said second buffer unit as current; and

a switching unit operable to switch the current designation of said designation unit, in accordance with the trigger signal, and

wherein said writing unit and said wait generating unit have, as an object, one of said buffer units which is not designated as current, and

one of said buffer units which is designated as current is operable to hold data to be stored from the processor.

15. The bus controller according to claim 10, further comprising:

a second buffer unit having the same configuration as said buffer unit which is referred to as a first buffer;

a designation unit operable to designate one of said first buffer unit and said second buffer unit as current; and

a switching unit operable to switch the current designation of said designation unit, in accordance with the trigger signal, and

wherein said writing unit and said wait generating unit have, as an object, one of said buffer units which is not designated as current, and

one of said buffer units which is designated as current is operable to hold data to be stored from the processor.