LOW POWER DIGITAL INTERFACE
First Claim
1. An interface circuit comprising:
- a buffer;
network communication circuitry connected tothe buffer,a data line of an external network, anda clock line of an external network configured to transmit a network clock signal; and
a bus communication circuitry connected tothe buffer,a data line of a bus of a host device comprising the interface circuit, anda clock line of the bus configured to transmit a bus clock signal,wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.
1 Assignment
0 Petitions
Accused Products
Abstract
This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.
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Citations
26 Claims
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1. An interface circuit comprising:
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a buffer; network communication circuitry connected to the buffer, a data line of an external network, and a clock line of an external network configured to transmit a network clock signal; and a bus communication circuitry connected to the buffer, a data line of a bus of a host device comprising the interface circuit, and a clock line of the bus configured to transmit a bus clock signal, wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A portable audio player comprising an interface circuit comprising:
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a buffer; network communication circuitry connected to the buffer, a data line of an external network, and a clock line of an external network configured to transmit a network clock signal; and a bus communication circuitry connected to the buffer, a data line of a bus of a host device comprising the interface circuit, and a clock line of the bus configured to transmit a bus clock signal, wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.
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16. A mobile telephone comprising an interface circuit comprising:
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a buffer; network communication circuitry connected to the buffer, a data line of an external network, and a clock line of an external network configured to transmit a network clock signal; and a bus communication circuitry connected to the buffer, a data line of a bus of a host device comprising the interface circuit, and a clock line of the bus configured to transmit a bus clock signal, wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.
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17. An interface circuit connected to an external network and a bus and configured to process communications between the external network and the bus, the interface circuit comprising:
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a first portion configured to operate according to a clock signal received from the external network; and a second portion configured to operate according to a clock signal received from the bus, wherein no part of the interface circuit relies on a dedicated internal high frequency clock signal. - View Dependent Claims (18, 20, 22)
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19. A method for operating a network interface comprising:
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receiving a network clock signal from an external network connection; receiving data from the external network connection; saving the received data in a buffer by utilizing the received networked clock signal; receiving a bus clock signal from a device bus connection; and reading the received data from the buffer and sending it to the bus connection by utilizing the received bus clock signal, wherein the method is performed without generating or using an internal dedicated high frequency clock signal. - View Dependent Claims (21)
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23. A method for operating a network interface comprising:
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receiving a bus clock signal from a device bus connection; receiving data from the bus connection; saving the received data in a buffer by utilizing the received bus clock signal; receiving a network clock signal from an external network connection; and reading the received data from the buffer and sending it to the network connection by utilizing the network clock signal, wherein the method is performed without generating or using an internal dedicated high frequency clock signal. - View Dependent Claims (24, 25, 26)
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Specification