Buffered Memory Module Supporting Two Independent Memory Channels
First Claim
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1. A memory system, comprising:
- a memory controller; and
a memory module coupled to the memory controller, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.
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Abstract
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.
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Citations
20 Claims
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1. A memory system, comprising:
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a memory controller; and a memory module coupled to the memory controller, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing system, comprising:
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a processor; and a memory controller coupled to the to the processor; a memory module coupled to the memory controller wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of accessing memory devices of a memory module, comprising:
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receiving, in one or more memory hub devices integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module, wherein the access request is received from a memory controller coupled to the memory module, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to the one or more memory hub devices of the memory module; selecting one of a first memory device data interface integrated in the one or more memory hub devices or a second memory device data interface integrated in the one or more memory hub devices, for performance of the access request; and accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface.
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Specification