Buffered Memory Module Supporting Two Independent Memory Channels

• US 20090063761A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 7,818,497 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1668 Details of memory controller

Abstract

A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.

Claims

1. A memory system, comprising:

a memory controller; and

a memory module coupled to the memory controller, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.

2. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

3. The memory system of claim 1, wherein the memory module comprises a single memory hub device, and wherein both of the at least two independent memory channels are coupled to the single memory hub device of the memory module.

4. The memory system of claim 3, wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices.

5. The memory system of claim 4, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface.

6. The memory system of claim 1, wherein the memory module comprises two memory hub devices, and wherein a first memory channel of the two independent memory channels is coupled to a first memory hub device of the two memory hub devices and the second memory channel of the two independent memory channels is coupled to a second memory hub device of the two memory hub devices.

7. The memory system of claim 6, wherein the first memory hub device comprises a first set of separate memory device data interfaces, each memory device data interface of the first set of separate memory device data interfaces providing a communication connection to a first separate set of memory devices, and wherein the second memory hub device comprises a second set of separate memory device data interfaces, each memory device data interface of the second set of separate memory device data interfaces providing a communication connection to a second separate set of memory devices.

8. The memory system of claim 1, wherein the one or more memory hub devices comprise:

a first memory device data interface integrated in the memory hub device, the first memory device data interface providing a communication interface with a first set of memory devices;

a second memory device data interface integrated in the memory hub device, the second memory device data interface providing a communication interface to communicate with a second set of memory devices;

a third memory device data interface integrated in the memory hub device, the third memory device data interface providing a communication interface to communicate with a third set of memory devices; and

a fourth memory device data interface integrated in the memory hub device, the fourth memory device data interface providing a communication interface to communicate with a fourth set of memory devices, wherein the first set of memory devices, the second set of memory devices, the third set of memory devices, and the fourth set of memory devices are separate from each other, and wherein the first, second, third, and fourth set of memory devices are communicated with by the memory hub device via the separate first, second, third, and fourth memory device data interfaces.

9. The memory system of claim 1, wherein the one or more memory hub devices each provide at least two separate memory device data interfaces for communicating with at least two separate sets of memory devices, each separate memory device being accessible by one of the at least two separate memory device data interfaces, and wherein access requests are processed via the at least two separate memory device data interfaces in parallel.

10. The memory system of claim 1, wherein the memory system is a main memory of a data processing device.

11. A data processing system, comprising:

a processor; and

a memory controller coupled to the to the processor;

a memory module coupled to the memory controller wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.

12. The data processing system of claim 11, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

13. The data processing system of claim 11, wherein the memory module comprises a single memory hub device, and wherein both of the at least two independent memory channels are coupled to the single memory hub device of the memory module.

14. The data processing system of claim 13, wherein the single memory hub device comprises four separate memory device data interfaces for communicating with four separate sets of memory devices.

15. The data processing system of claim 14, wherein a first memory channel of the at least two independent memory channels is coupled to a first memory device data interface and a second memory device data interface, and wherein a second memory channel of the at least two independent memory channels is coupled to a third memory device data interface and a fourth memory device data interface.

16. The data processing system of claim 11, wherein the memory module comprises two memory hub devices, and wherein a first memory channel of the two independent memory channels is coupled to a first memory hub device of the two memory hub devices and the second memory channel of the two independent memory channels is coupled to a second memory hub device of the two memory hub devices.

17. The data processing system of claim 16, wherein the first memory hub device comprises a first set of separate memory device data interfaces, each memory device data interface of the first set of separate memory device data interfaces providing a communication connection to a first separate set of memory devices, and wherein the second memory hub device comprises a second set of separate memory device data interfaces, each memory device data interface of the second set of separate memory device data interfaces providing a communication connection to a second separate set of memory devices.

18. The data processing system of claim 11, wherein the memory module comprises:

a first memory device data interface integrated in the memory hub device, the first memory device data interface providing a communication interface with a first set of memory devices;

a second memory device data interface integrated in the memory hub device, the second memory device data interface providing a communication interface to communicate with a second set of memory devices;

a third memory device data interface integrated in the memory hub device, the third memory device data interface providing a communication interface to communicate with a third set of memory devices; and

a fourth memory device data interface integrated in the memory hub device, the fourth memory device data interface providing a communication interface to communicate with a fourth set of memory devices, wherein the first set of memory devices, the second set of memory devices, the third set of memory devices, and the fourth set of memory devices are separate from each other, and wherein the first, second, third, and fourth set of memory devices are communicated with by the memory hub device via the separate first, second, third, and fourth memory device data interfaces.

19. The data processing system of claim 11, wherein each memory hub device of the at least one memory hub device provides at least two separate memory device data interfaces for communicating with at least two separate sets of memory devices of the plurality of memory devices, each separate memory device being accessible by one of the at least two separate memory device data interfaces, and wherein access requests are processed via the at least two separate memory device data interfaces in parallel.

20. A method of accessing memory devices of a memory module, comprising:

receiving, in one or more memory hub devices integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module, wherein the access request is received from a memory controller coupled to the memory module, wherein the memory controller is coupled to the memory module via at least two independent memory channels, and wherein the at least two independent memory channels are coupled to the one or more memory hub devices of the memory module;

selecting one of a first memory device data interface integrated in the one or more memory hub devices or a second memory device data interface integrated in the one or more memory hub devices, for performance of the access request; and

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface.