High Performance Pseudo Dynamic 36 Bit Compare

• US 20090063774A1
• Filed: 09/05/2007
• Published: 03/05/2009
• Est. Priority Date: 09/05/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuen H., Wang, Shie-ei, Lo, Kenneth M., Chen, Ann H.
• Granted Patent: US 7,996,620 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static logic elements. The output of each of these static comparators is then combined in a dynamic logic circuit to generate a dynamic late select output.

Claims

1. A set associative cache memory address comparator comprising in combination:

a plurality of comparator macros each comprised of static logic elements;

a bus to couple a different segment of said cache memory address and a bus to couple a corresponding segment of a cache memory tag address to an input of each of said plurality of comparator macros;

each of said plurality of comparator macros generating a predetermined binary output state if there is a bit by bit comparison between the cache memory segment and the tag memory segment coupled to its input;

a dynamic logic gate with all input from an output of each of said macros;

said dynamic logic gate generating a cache select signal if the output state from each said plurality of comparator macros is said predetermined binary output state.

2. A set associative cache memory address comparator as in claim 1 further including a dynamic latch to the cache select signal across a clock cycle boundary.

3. A set associative cache memory address comparator as in claim 1 further including a dynamic input multiplexer to said dynamic logic gate in order to provide selectable data and test operation.

4. A set associative cache memory address comparator as in claim 1 further including a high power output driver for said cache select signal and a separate low power output driver for a scan test output.

5. A set associative cache memory address comparator as in claim 2 further including a dynamic input multiplexer to said dynamic logic gate in order to provide selectable data and test operation.

6. A set associative cache memory address comparator as in claim 2 further including a high power output driver for said cache select signal and a separate low power output driver for a scan test output.

7. A set associative cache memory address comparator as in claim 3 further including a high power output driver for said cache select signal and a separate low power output driver for a scan test output.

19. A cache memory address comparator as in claim 1 wherein said dynamic logic gate includes a dynamic latch that is set to a standby state by a clock signal in its inactive state, a stack of series connected transistors each respectively controlled by an input from one of said macros, said series connected transistors switching said dynamic latch from said standby state when said clock signal is in its active sate and an input to each of said series connected transistors is in said predetermined binary output state, whereby the duration of a hit output of said comparator is determined by said clock signal.

20. A cache memory address comparator as in claim 19 wherein when said clock signal is in its inactive state inputs to the dynamic logic gate art ignored and the output of the dynamic logic gate is stable.

8. A method for generating a cache select signal in a set associative cache memory, including the steps of:

dividing a cache memory address into a plurality of cache address memory segments;

dividing a cache tag address into said plurality of tag address memory segments;

comparing each of said cache memory address segments with each corresponding ones of said tag memory address segments in a static comparison process to generate a predetermined binary output state from each comparison;

combining each result of the comparing step in a dynamic logic process to generate a cache select signal if each result of the comparing step is said predetermined output state.

9. A method for generating a cache select signal in a set associative cache memory as in claim 8 including the further step of generating holding said cache select signal across a clock cycle boundary.

10. A method for generating a cache select signal in a set associative cache memory as in claim 8 including the further step of generating a high power dynamic output for said cache select signal and generating a low power output for a scan test signal.

11. A method for generating a cache select signal in a set associative cache memory as in claim 9 including the further step of generating a high power dynamic output for said cache select signal ad generating a low power output for a scan test signal.

12. A cache memory address comparator comprising in combination:

means for dividing a cache memory address into a plurality of cache memory address segments;

means for dividing a cache tag address into said plurality of tag memory address segments;

means for statically comparing each of said cache memory address segments with each corresponding ones of said tag memory address segments process to generate a predetermined binary output state from each comparison;

means for dynamically combining each predetermined binary output state to generate a cache select signal if each result of the comparing step is said predetermined output state.

13. A cache memory address comparator as in claim 12 further including means to multiplex data and scan inputs to said means for dynamically combining.

14. A cache memory address comparator as in claim 12 further including means to dynamically latch to the cache select signal across a clock cycle boundary.

15. A cache memory address comparator as in claim 12 further including means for generating a high power output for said cache select signal and means for generating a low power output for a scan test signal.

16. A cache memory address comparator as in claim 13 further including means to dynamically latch to the cache select signal across a clock cycle boundary.

17. A cache memory address comparator as in claim 13 further including means for generating a high power output for said cache select sigil and means for generating a low power output for a scan test signal.

18. A cache memory address comparator as in claim 16 further including means for generating a high power output for said cache select signal and means for generating a low power output for a scan test signal.