System for Enhancing the Memory Bandwidth Available Through a Memory Module
First Claim
1. A memory system comprising:
- a memory hub device integrated in a memory module;
a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and
a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
-
Citations
25 Claims
-
1. A memory system comprising:
-
a memory hub device integrated in a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A memory module, comprising:
-
a memory hub device integrated into the memory module; a first set of memory devices integrated in the memory module and coupled to the memory hub device; a second set of memory devices integrated in the memory module and coupled to the memory hub device; a first memory device data interface integrated in the memory hub device through which the first set of memory devices are coupled to internal logic of the memory hub device; and a second memory device data interface integrated in the memory hub device through which the second set of memory devices are coupled to internal logic of the memory hub device, wherein the first set of memory devices are separate from the second set of memory devices and the first and the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. - View Dependent Claims (17)
-
-
18. A data processing system, comprising:
-
a processor; and a memory coupled to the processor, wherein the memory comprises at least one memory module, and wherein the at least one memory module comprises; a memory hub device integrated in a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
-
Specification