Buffered Memory Module Supporting Double the Memory Device Data Width in the Same Physical Space as a Conventional Memory Module

• US 20090063785A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 7,899,983 B2
• Time in Patent Office: Days
• US Class Current: 711/148
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10515 Stacked components
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.

Claims

1. A memory system, comprising:

a memory hub device integrated into a memory module;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.

2. The memory system of claim 1, wherein at least one of chip select signals, clock enable signals, calibration signals, or on-die termination signals of the first set of memory devices and the second set of memory devices are coupled together to the substrate.

3. The memory system of claim 1, wherein the second set of memory devices is stacked over the first set of memory devices.

4. The memory system of claim 1, wherein a first memory access request is processed via the first memory device data interface and a second memory access request is processed via the second memory device data interface at substantially a same time in a parallel manner using a chip select signal.

5. The memory system of claim 1, wherein the memory system further comprises:

a memory channel for communicating with the first set of memory devices and second set of memory devices via the memory hub device; and

a memory controller in communication with the memory channel, wherein the memory controller generates memory access requests, receives memory access requests, and responds to memory access requests.

6. The memory system of claim 1, wherein the memory hub device further comprises:

a memory hub controller coupled to the first memory device data interface and the second memory device data interface.

7. The memory system of claim 6, wherein the memory hub controller responds to access request packets from one of a memory controller external to the memory module or a downstream memory hub device of another memory module by responsively driving one or more of the first set of memory devices or the second set of memory devices using a memory device address and control bus and directing one of a read data flow selector or a write data flow selector.

8. The memory system of claim 7, wherein the memory hub controller drives the read data flow selector to a multiplexer of the memory hub device to select outputting read data directly, from one of the first memory device data interface or the second memory device data interface, or outputting read data from a read data queue.

9. The memory system of claim 7, wherein the memory hub controller drives the write data flow selector to a first multiplexer and a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device.

10. The memory system of claim 9, wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface.

11. The memory system of claim 6, wherein the memory hub controller, in response to a write access request packet, issues a first memory write access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory write access request to the second set of memory devices via the second memory device data interface.

12. The memory system of claim 6, wherein the memory hub controller, in response to a read access request packet, issues a first memory read access request to the first set of memory devices via the first memory device data interface and substantially immediately issues a second memory read access request to the second set of memory devices via the second memory device data interface.

13. The memory system of claim 12, wherein read data from the first memory read access request and the second memory read access request are directly transferred to the memory controller.

14. The memory system of claim 12, wherein read data from the first memory read access request and the second memory read access request are queued prior to be transferred to the memory controller.

15. The memory system of claim 1, wherein the memory system is part of a data processing device.

16. The memory system of claim 1, wherein the memory system is a main memory of a data processing device.

17. The memory system of claim 1, wherein the memory module is a dual in-line memory module (DIMM).

18. The memory system of claim 1, wherein the memory module is a single in-line memory module (SIMM).

19. A method of accessing memory devices of a memory module, comprising:

receiving, in a memory hub device integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices that are coupled to internal logic of the memory hub device or a second set of memory devices integrated in the memory module that are coupled to internal logic of the memory hub device;

selecting one of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the access request; and

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein;

the first memory device data interface communicates with the first set of memory devices,

the second memory device data interface communicates with the second set of memory devices,

the first set of memory devices are separate from the second set of memory devices,

the first memory device data interface is separate from the second memory device data interface, and

the first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.

20. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises at least one memory module, and wherein the at least one memory module comprises;

a memory hub device integrated in a memory module;

a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and

a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.