Buffered Memory Module Supporting Double the Memory Device Data Width in the Same Physical Space as a Conventional Memory Module
First Claim
1. A memory system, comprising:
- a memory hub device integrated into a memory module;
a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and
a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
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Abstract
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated into a memory module, a first memory device data interface integrated that communicates with a first set of memory devices and a second memory device data interface integrated that communicates with a second set of memory devices. In the memory system, the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module and the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate. In the memory system, data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
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Citations
20 Claims
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1. A memory system, comprising:
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a memory hub device integrated into a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of accessing memory devices of a memory module, comprising:
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receiving, in a memory hub device integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices that are coupled to internal logic of the memory hub device or a second set of memory devices integrated in the memory module that are coupled to internal logic of the memory hub device; selecting one of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the access request; and accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein; the first memory device data interface communicates with the first set of memory devices, the second memory device data interface communicates with the second set of memory devices, the first set of memory devices are separate from the second set of memory devices, the first memory device data interface is separate from the second memory device data interface, and the first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface, wherein the first set of memory devices are spaced in a first plane and coupled to a substrate of the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
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20. A data processing system, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises at least one memory module, and wherein the at least one memory module comprises; a memory hub device integrated in a memory module; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, wherein the second set of memory devices are spaced in a second plane above the first plane and coupled to the substrate, wherein data buses of the first set of memory devices are coupled to the substrate separately from data buses of the second set of memory devices.
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Specification