Buffered Memory Module with Multiple Memory Device Data Interface Ports Supporting Double the Memory Capacity
First Claim
1. A memory system, comprising:
- a memory controller; and
at least one memory module coupled to the memory controller, wherein each memory module of the at least one memory module comprises at least one memory hub device integrated in the memory module, and wherein the each memory hub device in the memory module comprises;
a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and
a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, and wherein;
the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces, andthe first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface.
2 Assignments
0 Petitions
Accused Products
Abstract
A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.
-
Citations
20 Claims
-
1. A memory system, comprising:
-
a memory controller; and at least one memory module coupled to the memory controller, wherein each memory module of the at least one memory module comprises at least one memory hub device integrated in the memory module, and wherein the each memory hub device in the memory module comprises; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, and wherein; the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces, and the first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A method of accessing memory devices of a memory module, comprising:
-
receiving, in a memory hub device integrated in the memory module, an access request for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module, wherein the access request is received from a memory controller coupled to the memory module; selecting one of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the access request; and accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein; the first memory device data interface communicates with the first set of memory devices, the second memory device data interface communicates with the second set of memory devices, the first set of memory devices are separate from the second set of memory devices, the first memory device data interface is separate from the second memory device data interface, and the first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface.
-
-
20. A data processing system, comprising:
-
a processor; and a memory controller coupled to the to the processor; a memory coupled to the memory controller, wherein the memory comprises at least one memory module and wherein the at least one memory module comprises; a memory hub device integrated in a memory module, wherein each memory hub device in the memory module comprises; a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module; and a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module, and wherein; the first set of memory devices are separate from the second set of memory devices and the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces, and the first memory device data interface and the second memory device data interface process access requests in parallel at substantially a same time, thereby increasing a bandwidth for accessing the memory devices relative to a memory module having a single memory device data interface
-
Specification