System for Data Processing Using a Multi-Tiered Full-Graph Interconnect Architecture

• US 20090063811A1
• Filed: 08/27/2007
• Published: 03/05/2009
• Est. Priority Date: 08/27/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Rajamony, Ramakrishnan, Arimilli, Lakshminarayana B., Seminaro, Edward J., Speight, William E.
• Granted Patent: US 8,140,731 B2
• Time in Patent Office: Days
• US Class Current: 712/10
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

Claims

1. A data processing system, comprising:

a plurality of processors coupled to one another to create a plurality of processor books;

the plurality of processor books coupled together to create a plurality of supernodes; and

the plurality of supernodes coupled together, wherein data is transmitted from one processor to another based on an addressing scheme specifying at least a supernode and a processor book associated with a target processor to which the data is to be transmitted.

2. The system of claim 1, wherein a subset of processors of the plurality of processors is associated with each processor book of the plurality of processor books, and wherein each processor within the processor book is directly coupled to each other processor within the processor book.

3. The system of claim 1, wherein a subset of processor books of the plurality of processor books is associated with each supernode of the plurality of supernodes, and wherein each processor book within the supernode is directly coupled to each other processor book within the supernode.

4. The system of claim 1, wherein each supernode within a subset of the plurality of supernodes is directly coupled to each other supernode within the subset of supernodes.

5. The system of claim 2, wherein the subset of processors comprises at least eight processors.

6. The system of claim 3, wherein the subset of processor books comprises at least sixteen processor books.

7. The system of claim 4, wherein the subset of the plurality of supernodes comprises at least five hundred and twelve supernodes.

8. The system of claim 1, wherein:

a subset of processors of the plurality of processors is associated with each processor book of the plurality of processor books, and wherein each processor within the processor book is directly coupled to each other processor within the processor book;

a subset of processor books of the plurality of processor books is associated with each supernode of the plurality of supernodes, and wherein each processor book within a supernode is directly coupled to each other processor book within the supernode; and

each supernode within a subset of the plurality of supernodes is directly coupled to each other supernode within the subset of supernodes.

9. The system of claim 8, wherein:

the subset of processors are coupled to each other by a set of first buses;

the subset of processor books are coupled to each other by a set of second buses;

the subset of supernodes are coupled to each other by a set of third buses; and

data is routed from one processor in a first supernode to another processor in a second supernode using at least one routing table data structure that specifies at least one first bus, at least one second bus, and at least one third bus over which the data is to be transmitted.

10. The system of claim 9, wherein at least one of the set of first buses, the set of second buses, or the set of third buses are cache coherent buses.

11. The system of claim 9, wherein at least one of the set of first buses, the set of second buses, or the set of third buses are non-cache coherent buses.

12. The system of claim 1, wherein each processor in the plurality of processors of a first processor book comprises at least two communication links for coupling the processor to at least two other processor books in a same supernode as the supernode in which the first processor book is provided.

13. The system of claim 1, wherein each processor in the plurality of processors of a processor book within a supernode comprises at least four communication links for coupling the processor to at least four other supernodes in the plurality of supernodes.

14. The system of claim 1, wherein each processor book in the plurality of processor books of a supernode comprises at least thirty-two communication links for coupling the processor book to at least thirty-two other supernodes in the plurality of supernodes.

15. The system of claim 1, wherein each supernode of the plurality of supernodes comprises at least five hundred and eleven communication links for coupling the supernode to at least five hundred and eleven other supernodes in the plurality of supernodes.

16. The system of claim 1, wherein each processor of the plurality of processors has an integrated switch, and wherein the integrated switch in the processor implements the addressing scheme to route data from that processor to at least one other processor in the plurality of processors.

17. The system of claim 16, wherein the integrated switch in each processor of the plurality of processors utilizes one or more routing table data structures that specify pathways from the processor to other processors in the data processing system based on a supernode identifier, a processor book identifier, and a processor chip identifier.

18. The system of claim 1, wherein each processor in a processor book is directly coupled to two other processors in other processor books within a same supernode, the two other processors each being in a separate other processor book.

19. The system of claim 1, wherein each processor in a processor book is directly coupled to four other processors in other processor books within different supernodes, the four other processors each being in a separate other processor book in separate other supernodes.

20. The system of claim 1, wherein each processor has a plurality of cores.

21. The system of claim 20, wherein the cores are homogeneous.

22. The system of claim 20, wherein the cores are heterogeneous.

23. The system of claim 1, wherein each processor has a host fabric interface, and wherein the host fabric interface is utilized to process Message Passing Interface (MPI) tasks.

24. The system of claim 1, wherein each processor has a collective acceleration unit for performing collective operations in conjunction with one or more other processors.

25. The system of claim 9, wherein the set of first buses are cache coherent, wherein the set of second buses are non-cache-coherent buses, and wherein the set of third buses are non-cache-coherent buses.

26. The system of claim 1, wherein the data processing system utilizes a multi-tiered full-graph interconnect architecture.