×

PROCESSOR, DATA TRANSFER UNIT, MULTICORE PROCESSOR SYSTEM

  • US 20090063812A1
  • Filed: 07/14/2008
  • Published: 03/05/2009
  • Est. Priority Date: 08/29/2007
  • Status: Active Grant
First Claim
Patent Images

1. A processor comprising:

  • a CPU capable of performing predetermined arithmetic and logical processing;

    a memory accessible by the CPU; and

    a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU, the data transfer unit including;

    a command chain unit for continuously performing data transfer by execution of a preset command chain; and

    a retry controller for executing retry processing in case a transfer error occurs during data transfer by the command chain unit,wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×