PROCESSOR, DATA TRANSFER UNIT, MULTICORE PROCESSOR SYSTEM
First Claim
1. A processor comprising:
- a CPU capable of performing predetermined arithmetic and logical processing;
a memory accessible by the CPU; and
a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU, the data transfer unit including;
a command chain unit for continuously performing data transfer by execution of a preset command chain; and
a retry controller for executing retry processing in case a transfer error occurs during data transfer by the command chain unit,wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain.
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Accused Products
Abstract
A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.
14 Citations
12 Claims
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1. A processor comprising:
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a CPU capable of performing predetermined arithmetic and logical processing; a memory accessible by the CPU; and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU, the data transfer unit including; a command chain unit for continuously performing data transfer by execution of a preset command chain; and a retry controller for executing retry processing in case a transfer error occurs during data transfer by the command chain unit, wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain. - View Dependent Claims (2, 3, 4)
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5. A data transfer unit capable of controlling data transfer in accordance with a CPU capable of performing predetermined arithmetic and logical processing by substituting for the CPU, the data transfer unit comprising:
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a command chain unit for continuously performing data transfer by execution of a preset command chain; and a retry controller for performing a retry-processing in case a transfer error occurs during data transfer by the command chain unit, wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain. - View Dependent Claims (6, 7, 8)
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9. A multicore processor system comprising a plurality of processor cores, each capable of performing predetermined arithmetic and logical processing, and a common memory shared by the plurality of the processor cores,
wherein the processor core includes: -
a CPU capable of performing predetermined arithmetic and logical processing; a core internal memory accessible by the CPU; and a data transfer unit capable of controlling data transfer between the core internal memory and the common memory, by substituting for the CPU, the data transfer unit includes; a command chain unit for continuously performing data transfer by execution of a preset command chain; and a retry controller for performing a retry-processing in case a transfer error occurs during data transfer by the command chain unit, wherein the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain. - View Dependent Claims (10, 11, 12)
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Specification