System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture

• US 20090063880A1
• Filed: 08/27/2007
• Published: 03/05/2009
• Est. Priority Date: 08/27/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Lakshminarayana B, Arimilli, Ravi K., Rajamony, Ramakrishnan
• Granted Patent: US 7,809,970 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 9/5088 involving task migration

Abstract

A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.

Claims

1. A method, in a data processing system, for performing a Message Passing Interface (MPI) job, the data processing system comprising a plurality of sup emodes, the plurality of supernodes comprising a plurality of processor books, and the plurality of processor books comprising a plurality of processors, the method comprising:

receiving, in a first processor chip, a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system, the arrival signals identifying when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job;

responsive to receiving the set of arrival signals from the set of processor chips, identifying, in the first processor chip, a fastest processor chip of the set of processor chips whose arrival signal arrived first; and

modifying an operation of the fastest processor chip based on the identification of the fastest processor chip, wherein the set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.

2. The method of claim 1, wherein at least one processor chip in the set of processor chips is in a different processor book from at least one other processor chip in the set of processor chips.

3. The method of claim 2, wherein the at least one processor chip in the set of processor chips is in a different supernode from the at least one other processor chip in the set of processor chips.

4. The method of claim 1, wherein modifying the operation of the fastest processor chip comprises controlling the fastest processor chip to reduce power consumption of the fastest processor chip.

5. The method of claim 1, wherein modifying the operation of the fastest processor chip comprises controlling the fastest processor chip to reduce heat dissipation of the fastest processor chip by utilizing a lower operating voltage or operating frequency.

6. The method of claim 1, further comprising:

responsive to receiving the set of arrival signals from the set of processor chips, identifying, in the first processor chip, a slowest processor chip of the set of processor chips whose arrival signal arrived last; and

modifying an operation of the slowest processor chip based on the identification of the slowest processor chip.

7. The method of claim 6, wherein modifying the operation of the slowest processor chip comprises controlling the slowest processor chip to permit dissipation of an increased amount of thermal energy by utilizing a higher operating voltage or operating frequency.

8. The method of claim 6, wherein modifying the operation of the fastest processor chip and modifying the operation of the slowest processor chip comprises reallocating resources associated with the fastest processor chip such that they are associated with the slowest processor chip.

9. The method of claim 8, wherein the resources comprise at least one of memory bandwidth, cache capacity, cache bandwidth, number of cache sets available to each task executing on the processor chip, a simultaneous multithreading (SMT) thread priority, number of physical registers available for register renaming, bus bandwidth, number of functional units, or number of translation lookaside buffer (TLB) entries.

10. The method of claim 1, wherein modifying the operation of the fastest processor chip comprises modifying a mapping of tasks to the set of processor chips so as to map an increased number of tasks to the fastest processor chip.

11. The method of claim 1, wherein the method is implemented by a host fabric interface of the first processor chip.

12. A computer program product, for performing a Message Passing Interface (MPI) job, comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed in a first processor chip of a data processing system, causes the first processor chip to:

receive a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system, the arrival signals identifying when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job;

responsive to receiving the set of arrival signals from the set of processor chips, identify, in the first processor chip, a fastest processor chip of the set of processor chips whose arrival signal arrived first; and

modify an operation of the fastest processor chip based on the identification of the fastest processor chip, wherein the set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system and wherein the data processing system comprises a plurality of supernodes, the plurality of supernodes comprising a plurality of processor books, and the plurality of processor books comprising a plurality of processors.

13. The computer program product of claim 12, wherein at least one processor chip in the set of processor chips is in a different processor book from at least one other processor chip in the set of processor chips.

14. The computer program product of claim 12, wherein modifying the operation of the fastest processor chip comprises controlling the fastest processor chip to reduce power consumption of the fastest processor chip.

15. The computer program product of claim 12, wherein modifying the operation of the fastest processor chip comprises controlling the fastest processor chip to reduce heat dissipation of the fastest processor chip by utilizing a lower operating voltage or operating frequency.

16. The computer program product of claim 12, wherein the computer readable program further causes the first processor to:

responsive to receiving the set of arrival signals from the set of processor chips, identify, in the first processor chip, a slowest processor chip of the set of processor chips whose arrival signal arrived last; and

modify an operation of the slowest processor chip based on the identification of the slowest processor chip.

17. The computer program product of claim 12, wherein the computer readable program is executed by a host fabric interface of the first processor chip.

20. The data processing system of claim 16, wherein modifying the operation of the fastest processor chip comprises controlling the fastest processor chip to reduce at least one of power consumption of the fastest processor chip or heat dissipation of the fastest processor chip by utilizing a lower operating voltage or operating frequency.

18. A data processing system for performing a Message Passing Interface (MPI) job, comprising:

a first processor; and

a memory coupled to the first processor, wherein the memory comprises instructions which, when executed by the first processor, cause the first processor to;

receive a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system, the arrival signals identifying when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job;

responsive to receiving the set of arrival signals from the set of processor chips, identify, in the first processor chip, a fastest processor chip of the set of processor chips whose arrival signal arrived first; and

modify an operation of the fastest processor chip based on the identification of the fastest processor chip, wherein the set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system and wherein the data processing system comprises a plurality of supernodes, the plurality of supernodes comprising a plurality of processor books, and the plurality of processor books comprising a plurality of processors.

19. The data processing system of claim 18, wherein at least one processor chip in the set of processor chips is in a different processor book from at least one other processor chip in the set of processor chips.