Low-overhead/power-saving processor synchronization mechanism, and applications thereof

• US 20090063881A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Abandoned Application

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Stephens, Nigel John
• Application Number:
  US11/896,424
• Publication Number:
  US 20090063881A1
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A low-overhead/power-saving processor synchronization mechanism, and applications thereof. In an embodiment, the present invention provides a processor having a load-linked register. The processor implements instructions related to the load-linked register. A first instruction, when executed by the processor, causes the processor to load a first value specified by the first instruction in a first register of a register file and to load a second value in the load-linked register. A second instruction, when executed by the processor, causes the processor to suspend execution of a stream of instructions associated with the load-linked register if the second value in the load-linked register is unaltered until the second value in the load-linked register is altered. A third instruction, when executed by the processor, causes the processor to conditionally move a third value to a memory location specified by the third instruction and to move a value representing the state of the load-linked register to the third register.

Claims

1. A processor, comprising:

a load-linked register,

wherein execution of a first instruction by the processor causes the processor to suspend execution of a stream of instructions associated with the load-linked register if a first value is stored in the load-linked register.

2. The processor of claim 1, further comprising:

a register file that includes a plurality of registers,

wherein execution of a second instruction by the processor causes the processor to load a memory value specified by the second instruction in a first register of the register file and to load a value in the load-linked register.

3. The processor of claim 2, wherein execution of a third instruction by the processor causes the processor to conditionally move a value to a memory location specified by the third instruction if the value in the load-linked register has not been altered since execution of the second instruction, and to load a value representing the state of the load-linked register to a register of the register file.

4. The processor of claim 3, wherein the value loaded from the load-linked register to the register of the register file is zero-extended.

5. The processor of claim 1, wherein the load-linked register is a one-bit or a two-bit register.

6. The processor of claim 1, further comprising:

a second load-linked register.

7. A system, comprising:

a processor that includes

a register file that includes a plurality of registers, and

a load-linked register,

wherein execution of a first instruction by the processor causes the processor to load a first value specified by the first instruction in a first register of the register file and to load a second value in the load-linked register, and

wherein execution of a second instruction by the processor causes the processor to suspend execution of a stream of instructions associated with the load-linked register until the value in the load-linked register is different from the second value; and

a memory coupled to the processor.

8. The system of claim 7, wherein the load-linked register is a one-bit or a two-bit register.

9. The system of claim 7, wherein execution of the first instruction loads a value of one in the load-linked register.

10. The system of claim 7, wherein execution of a third instruction by the execution unit causes the processor to load a value representing the value stored in the load-linked register to a register of the register file.

11. The system of claim 7, wherein the processor further includes a second register file that includes a plurality of registers and a second load-linked register.

12. A control method for a computing system, comprising:

(1) executing a first instruction that loads a first value specified by the first instruction in a first register of a register file and that loads a second value in a load-linked register;

(2) executing a second instruction that suspends execution of a stream of instructions associated with the load-linked register until the value in the load-linked register is different from the second value; and

(3) executing a third instruction that conditionally moves a third value to a memory location specified by the third instruction if the value in the load-linked register has not been altered since execution of the first instruction, and that loads a representation of the value stored in the load-linked register to a register of the register file.

13. The method of claim 12, wherein (1) comprises:

loading a value of one in the load-linked register.

14. The method of claim 12, further comprising:

(4) powering-down at least a portion of a processor as a result of executing the second instruction.

15. A control method for a computing system, comprising:

(1) executing a first instruction that loads a first value specified by the first instruction in a first register of a register file and that loads a second value in a load-linked register;

(2) executing a second instruction that suspends execution of a stream of instructions associated with the load-linked register until the second value in the load-linked register is altered; and

(3) powering-down a portion of a processor as a result of executing the second instruction.

16. The method of claim 15, wherein (1) comprises:

loading a value of one in the load-linked register.

17. The method of claim 15, further comprising:

(4) powering-up the portion of the processor when the second value in the load-linked register is altered.

18. A computer method for implementing a lock, comprising:

(1) executing a sequence of instructions that cause a multithreading processor to suspend execution of a selected thread of instructions in response to a value stored in a hardware controlled load-linked register; and

(2) resuming execution of the suspended stream of instructions in response to a change in the value stored in the load-linked register.

19. The method of claim 18, wherein (1) comprises executing a YIELDLL instruction.

20. The method of claim 18, wherein (1) comprises executing an instruction that is capable of running on any MIPS instruction set architecture compatible processor.