System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture
First Claim
1. A system, comprising:
- a plurality of processor chips, each processor chip in the plurality of processor chips having heartbeat signal generation logic; and
at least one communication link between the plurality of processor chips, wherein;
the at least one communication link couples the plurality of processor chips into a computing cluster,heartbeat signal generation logic of a first processor chip synchronizes a first heartbeat signal transmitted by the first processor chip with second heartbeat signals of other second processor chips in the plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time, andthe first processor chip in the plurality of processor chips generates an internal system clock signal based on the first heartbeat signal such that, through synchronization of the first heartbeat signal with the second heartbeat signals of the other second processor chips of the plurality of processor chips, the internal system clock signals of each processor chip of the plurality of processor chips are synchronized.
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Abstract
A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.
120 Citations
25 Claims
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1. A system, comprising:
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a plurality of processor chips, each processor chip in the plurality of processor chips having heartbeat signal generation logic; and at least one communication link between the plurality of processor chips, wherein; the at least one communication link couples the plurality of processor chips into a computing cluster, heartbeat signal generation logic of a first processor chip synchronizes a first heartbeat signal transmitted by the first processor chip with second heartbeat signals of other second processor chips in the plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time, and the first processor chip in the plurality of processor chips generates an internal system clock signal based on the first heartbeat signal such that, through synchronization of the first heartbeat signal with the second heartbeat signals of the other second processor chips of the plurality of processor chips, the internal system clock signals of each processor chip of the plurality of processor chips are synchronized. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A processor chip, comprising:
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one or more processors; and heartbeat signal generation logic, wherein; the heartbeat signal generation logic synchronizes a first heartbeat signal transmitted by the processor chip with second heartbeat signals of other second processor chips in a plurality of processor chips such that each processor chip in the plurality of processor chips transmits a heartbeat signal at approximately a same time, and the processor chip generates an internal system clock signal for use by the one or more processors based on the first heartbeat signal such that, through synchronization of the first heartbeat signal with the second heartbeat signals of the other second processor chips of the plurality of processor chips, the internal system clock signals of each processor chip of the plurality of processor chips are synchronized. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification