System for Performing Error Correction Operations in a Memory Hub Device of a Memory Module

• US 20090063922A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 8,082,482 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices. The memory hub device also comprises error correction logic integrated in the memory hub device and coupled to the link interface. The error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices; and

error correction logic integrated in the memory hub device and coupled to the link interface, wherein the error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.

2. The memory system of claim 1, wherein the error correction logic, for read data received from the set of memory devices, checks the read data from the set of memory devices for errors using stored error code bits prior to transmitting the read data and generates an error signal if the read data contains an error that cannot be corrected.

3. The memory system of claim 1, wherein the error correction logic comprises error correction code generation logic that generates error correction code data based on write data received from the external memory controller via the link interface.

4. The memory system of claim 1, wherein the error correction logic comprises logic that corrects read data received from the set of memory devices prior to transmitting the read data to the external memory controller via the link interface.

5. The memory system of claim 1, wherein, in response to receiving a read access request from the external memory controller, the memory hub controller responds by driving memory devices in the set of memory devices using a memory device address and control bus to read out data from the set of memory devices, and wherein the data read out of the set of memory devices is provided to the error correction logic.

6. The memory system of claim 5, wherein:

the data read out of the set of memory devices includes error correction bits previously generated for the data; and

the error correction logic generates check bits based on the data and the error correction bits in the data read out of the set of memory devices, the check bits indicating if the data read out of the set of memory devices is correct.

7. The memory system of claim 6, wherein if the error correction logic is able to be corrected, then the error correction logic generates pointers to correct data for bits of the data read out of the set of memory devices that are determined to be incorrect.

8. The memory system of claim 6, wherein if the error correction logic determines that the data read out of the set of memory devices contains errors that are not correctable, then the data read out of the set of memory devices is output from the memory hub device to the external memory controller along with an error signal indicating the data read out of the set of memory devices to be invalid.

9. The memory system of claim 1, wherein, in response to receiving a write access request from the external memory controller, write data associated with the write access request is provided to error correction code generation logic of the error correction logic of the memory hub controller, and wherein the error correction code generation logic generates error correction bits based on the write data and adds the error correction bits to the write data thereby forming modified write data.

10. The memory system of claim 9, wherein the modified write data having the error correction bits is sent to the set of memory devices via the memory device data interface under control of the memory hub controller.

11. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

12. The memory system of claim 1, wherein the memory module is part of a data processing device.

13. The memory system of claim 1, wherein the memory module is part of a main memory of a data processing system.

14. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

a link interface integrated into the memory hub device that provides a communication pathway between an external memory controller and the set of memory devices; and

error correction logic integrated in the memory hub device and coupled to the link interface, wherein the error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.

15. The data processing system of claim 14, wherein the error correction logic, for read data received from the set of memory devices, checks the read data from the set of memory devices for errors using stored error code bits prior to transmitting the read data and generates an error signal if the read data contains an error that cannot be corrected.

16. The data processing system of claim 14, wherein the error correction logic comprises error correction code generation logic that generates error correction code data based on write data received from the external memory controller via the link interface.

17. The data processing system of claim 14, wherein the error correction logic comprises logic that corrects read data received from the set of memory devices prior to transmitting the read data to the external memory controller via the link interface.

18. The data processing system of claim 14, wherein, in response to receiving a read access request from the external memory controller, the memory hub controller responds by driving memory devices in the set of memory devices using a memory device address and control bus to read out data from the set of memory devices, and wherein the data read out of the set of memory devices is provided to the error correction logic.

19. The data processing system of claim 18, wherein:

the data read out of the set of memory devices includes error correction bits previously generated for the data; and

the error correction logic generates check bits based on the data and the error correction bits in the data read out of the set of memory devices, the check bits indicating if the data read out of the set of memory devices is correct.

20. The data processing system of claim 19, wherein if the error correction logic is able to be corrected, then the error correction logic generates pointers to correct data for bits of the data read out of the set of memory devices that are determined to be incorrect.

21. The data processing system of claim 19, wherein if the error correction logic determines that the data read out of the set of memory devices contains errors that are not correctable, then the data read out of the set of memory devices is output from the memory hub device to the external memory controller along with an error signal indicating the data read out of the set of memory devices to be invalid.

22. The data processing system of claim 14, wherein, in response to receiving a write access request from the external memory controller, write data associated with the write access request is provided to error correction code generation logic of the error correction logic of the memory hub controller, and wherein the error correction code generation logic generates error correction bits based on the write data and adds the error correction bits to the write data thereby forming modified write data.

23. The data processing system of claim 22, wherein the modified write data having the error correction bits is sent to the set of memory devices via the memory device data interface under control of the memory hub controller.

24. The data processing system of claim 14, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).