System and Method for Performing Error Correction at a Memory Device Level that is Transparent to a Memory Channel

• US 20090063923A1
• Filed: 08/31/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Granted Patent: US 8,086,936 B2
• Time in Patent Office: Days
• US Class Current: 714/746
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems

Abstract

A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises first error correction logic provided in write logic integrated in the memory hub device. The memory hub device comprises second error correction logic provided in read logic integrated in the memory hub device. The first error correction logic and the second error correction logic performs error correction operations on data transferred between a link interface and the set of memory devices. The memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code.

Claims

1. A memory system comprising:

a memory hub device integrated in a memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices;

second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; and

a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.

2. The memory system of claim 1, wherein the first error correction logic checks the read data from the set of memory devices for errors using stored error code bits prior to transmitting the read data and generates an error signal if the read data contains an error that cannot be corrected.

3. The memory system of claim 2, wherein the first error correction logic comprises first error correction code generation logic, and wherein the first error correction code generation logic generates an error correction codeword that is added to the read data before transmitting the read data to the external memory controller via the link interface.

4. The memory system of claim 1, wherein the second error correction logic checks the write data from the link interface for errors prior to transmitting the write data to the set of memory devices.

5. The memory system of claim 4, wherein the second error correction logic comprises second error correction code generation logic, and wherein the second error correction code generation logic generates an error correction codeword that is added to the write data before transmitting the write data to the set of memory devices.

6. The memory system of claim 5, wherein the second error correction logic stores the write data in a write data queue along with a tag indicating the write data to be invalid if the second error correction logic determines that the write data contains an error that is not correctable by the second error correction logic.

7. The memory system of claim 5, wherein the second error correction logic removes error correction information from the write data before transmitting the write data to the error correction code generation logic.

8. The memory system of claim 1, wherein the first error correction logic and the second error correction logic comprises logic that corrects data prior to outputting the data.

9. The memory system of claim 1, wherein, in response to receiving a read access request from the external memory controller, the memory hub controller responds by driving memory devices in the set of memory devices using a memory device address and control bus to read out data from the set of memory devices, and wherein the data read out of the set of memory devices is provided to the error correction logic.

10. The memory system of claim 2, wherein:

the read data includes error correction bits previously generated for the data,

the first error correction logic generates check bits based on the data and the error correction bits in the read data, the check bits indicating if the read data is correct,

if the first error correction logic is able to be corrected, then the error correction logic generates pointers to correct data for bits of the read data that are determined to be incorrect, and

if the first error correction logic determines that the read data contains errors that are not correctable, then the read data is output from the memory hub device to the external memory controller along with an error signal indicating the read data to be invalid.

11. The memory system of claim 1, wherein the memory module is one of a dual in-line memory module (DIMM) or a single in-line memory module (SIMM).

12. The memory system of claim 1, wherein the memory module is part of a data processing device.

13. A data processing system, comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises one or more memory modules, each memory module comprising;

a memory hub device integrated in the memory module; and

a set of memory devices coupled to the memory hub device, wherein the memory hub device comprises;

first error correction logic provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices;

second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices; and

a link interface that provides a communication pathway between the memory hub device and an external memory controller, wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices, and wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel.

14. The data processing system of claim 13, wherein the first error correction logic checks the read data from the set of memory devices for errors using stored error code bits prior to transmitting the read data and generates an error signal if the read data contains an error that cannot be corrected.

15. The data processing system of claim 14, wherein the first error correction logic comprises a first error correction code generation logic, and wherein the first error correction code generation logic generates an error correction codeword that is added to the read data before transmitting the read data to the external memory controller via the link interface.

16. The data processing system of claim 13, wherein the second error correction logic checks the write data from the link interface for errors prior to transmitting the write data to the set of memory devices.

17. The data processing system of claim 16, wherein the second error correction logic comprises a second error correction code generation logic, and wherein the second error correction code generation logic generates an error correction codeword that is added to the write data before transmitting the write data to the set of memory devices.

18. The data processing system of claim 17, wherein the second error correction logic stores the write data in a write data queue along with a tag indicating the write data to be invalid if the second error correction logic determines that the write data contains an error that is not correctable by the second error correction logic.

19. The data processing system of claim 17, wherein the second error correction logic removes error correction information from the write data before transmitting the write data to the error correction code generation logic.

20. A method for performing error correction operations in a memory module, comprising:

receiving, in a memory hub device integrated in the memory module, an access request for accessing a set of memory devices of the memory module coupled to the memory hub device;

transferring data between a link interface of the memory hub device and the set of memory devices; and

performing, by first error correction logic and second error correction logic integrated in the memory hub device, one or more error correction operations on the data transferred between the link interface and the set of memory devices,

wherein the first error correction logic and the second error correction logic performs error correction operations on data transferred between the link interface and the set of memory devices,

wherein the memory hub device transmits and receives data via a memory channel between the external memory controller and the link interface without any error correction code, thereby reducing an amount of bandwidth used on the memory channel,

wherein the first error correction logic is provided in write logic integrated in the memory hub device, the write logic providing a data path for writing data to the set of memory devices, and

wherein the second error correction logic provided in read logic integrated in the memory hub device, the read logic providing a data path for reading data from the set of memory devices.