MULTI-CHANNEL MEMORY SYSTEM INCLUDING ERROR CORRECTION DECODER ARCHITECTURE WITH EFFICIENT AREA UTILIZATION
First Claim
1. A memory system, comprising:
- at least two memory devices; and
a memory controller having at least first and second communication channels each for communicating data with at least one of the memory devices, the memory controller comprising,at least first and second error detectors corresponding to the first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of the memory devices; and
an error corrector adapted to correct errors detected by each of the at least first and second error detectors.
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Abstract
A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.
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Citations
38 Claims
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1. A memory system, comprising:
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at least two memory devices; and a memory controller having at least first and second communication channels each for communicating data with at least one of the memory devices, the memory controller comprising, at least first and second error detectors corresponding to the first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of the memory devices; and an error corrector adapted to correct errors detected by each of the at least first and second error detectors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A memory system, comprising:
a memory controller having a first input port for communication with a first memory device via a first communication channel, a second input port for communication with a second memory device via a second communication channel, and an error decoder that is multiplexed for decoding data received from both the first and the second communication channels. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method of processing data received from at least two memory devices via at least two corresponding communication channels, the method comprising:
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detecting errors in a first data set received via a first communication channel while detecting errors in a second data set received via a second communication channel; and correcting the detected errors in the first data set and then subsequently correcting errors in the second data set. - View Dependent Claims (21, 22, 23, 24, 25)
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26. An error decoder, comprising:
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at least first and second error detectors corresponding to first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of memory devices; and an error corrector adapted to correct errors detected by each of the at least first and second error detectors. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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Specification