COMPILER FOR GENERATING AN EXECUTABLE COMPRISING INSTRUCTIONS FOR A PLURALITY OF DIFFERENT INSTRUCTION SETS

• US 20090064095A1
• Filed: 08/29/2007
• Published: 03/05/2009
• Est. Priority Date: 08/29/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Granted Patent: US 8,561,037 B2
• Time in Patent Office: Days
• US Class Current: 717/106
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor'"'"'s instruction set to be dynamically reconfigured.

Claims

1. A method comprising:

receiving, by a compiler, source code for a software application; and

processing, by the compiler, the source code to generate an executable image that comprises a first portion of instructions for a first processor instruction set and a second portion of instructions for a second processor instruction set that is different from said first processor instruction set.

2. The method of claim 1 further comprising:

determining at least said second processor instruction set for which said second portion of instructions is to be generated.

3. The method of claim 2 wherein said determining comprises:

selecting one of a plurality of predefined processor instruction sets.

4. The method of claim 3 wherein said plurality of predefined processor instruction sets comprise at least one of the following:

a vector instruction set designed for efficiently processing 64-bit floating point operations;

a vector instruction set designed for efficiently processing 32-bit floating point operations; and

an instruction set designed for efficiently processing cryptography-related operations.

5. The method of claim 2 wherein said determining comprises:

receiving, by the compiler, designation of one of a plurality of predefined processor instruction sets.

6. The method of claim 5 wherein said designation is included in said source code.

7. The method of claim 5 wherein said receiving comprises:

receiving said designation from a user via a user interface of said compiler.

8. The method of claim 2 wherein said determining comprises:

analyzing, by the compiler, the received source code for autonomously determining one of a plurality of predefined processor instruction sets.

9. The method of claim 8 wherein said analyzing comprises:

analyzing types of operations encountered in the source code; and

determining said one of the plurality of predefined processor instruction sets that enhances performance of at least a portion of the types of operations encountered.

10. The method of claim 1 wherein a target system on which the executable image is to be executed comprises a host processor having said first processor instruction set as a fixed instruction set and a heterogeneous co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, and wherein the method comprises:

selecting said second processor instruction set from said plurality of predefined processor instruction sets.

11. The method of claim 10 further comprising:

generating, within the executable image, an identification of the at least one of the plurality of predefined processor instruction sets for which instructions are included in the executable image.

12. The method of claim 1 further comprising:

performing, by a machine-independent optimizer of the compiler, optimizations to enhance performance of the executable image; and

determining, by a machine-dependent optimizer of the compiler, at least said second processor instruction set for which said second portion of instructions is to be generated.

13. A method comprising:

receiving, by a compiler, source code for a software application;

processing, by the compiler, the source code to generate an executable image that comprises instructions for execution on a multi-processor system having a plurality of heterogeneous processors, wherein the instructions comprise a first portion of instructions for a first processor instruction set and a second portion of instructions for a second processor instruction set that is different from said first processor instruction set.

14. The method of claim 13 wherein the heterogeneous processors comprise a host processor having said first processor instruction set and a co-processor having said second processor instruction set.

15. The method of claim 13 wherein said heterogeneous processors comprise a host processor having said first processor instruction set and a co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, said method comprising:

selecting said second processor instruction set from said plurality of predefined processor instruction sets.

16. The method of claim 15 further comprising,

generating, within the executable image, an identification of the selected second processor instruction set.

17. The method of claim 15 wherein said plurality of predefined processor instruction sets comprise at least one of the following:

a vector instruction set designed for efficiently processing 64-bit floating point operations;

a vector instruction set designed for efficiently processing 32-bit floating point operations; and

an instruction set designed for efficiently processing cryptography-related operations.

18. The method of claim 13 further comprising:

performing, by a machine-independent optimizer of the compiler, optimizations to enhance performance of the executable image; and

determining, by a machine-dependent optimizer of the compiler, at least said second processor instruction set for which said second portion of instructions is to be generated.

19. A compiler comprising:

front-end for receiving source code for a software application;

code generator for processing the source code to generate, in an executable image, instructions for a first processor instruction set and instructions for a second processor instruction set that is different from said first processor instruction set.

20. The compiler of claim 19 further comprising:

machine-independent optimizer for performing optimizations to enhance performance of the executable image; and

machine-dependent optimizer for determining at least said second processor instruction set.

21. The compiler of claim 20 wherein said optimizations comprise at least one of strength reduction and common sub-expression elimination.

22. The compiler of claim 19 further comprising:

machine-dependent optimizer for determining for which of a plurality of predefined processor instruction sets instructions are to be generated for inclusion in said executable image.

23. The compiler of claim 19 wherein a target system on which the executable image is to be executed comprises a host processor having a fixed instruction set and a heterogeneous co-processor having reconfigurable logic for dynamically reconfiguring the co-processor'"'"'s instruction set to be any of a plurality of predefined processor instruction sets, and wherein the compiler comprises:

said code generator for processing the source code to generate, in the executable images instructions for the fixed instruction set of the host processor and instructions for at least one of the plurality of predefined processor instruction sets with which the co-processor can be reconfigured.

24. The compiler of claim 23 further comprising:

generating, within the executable image, an identification of the at least one of the plurality of predefined processor instruction sets for which instructions are included in the executable image.

25. The compiler of claim 19 wherein the front-end is operable for receiving said source code coded in any of a plurality of different source code languages and generate an internal representation of the source for processing within the compiler.