TEST-KEY FOR CHECKING INTERCONNECT AND CORRESPONDING CHECKING METHOD

• US 20090065775A1
• Filed: 11/18/2008
• Published: 03/12/2009
• Est. Priority Date: 08/29/2005
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Cheng, Rui-Huang, Cheng, Yeh-Sheng, Liao, Shu-Yun, Lu, Hsin-Yu, Chien, Chih-Ying, Wang, Hsueh-Wen
• Granted Patent: US 8,278,765 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48

Abstract

A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Claims

1. A test key for checking an interconnect structure, comprising:

a contiguous metal line; and

a plurality of conductive plugs on the contiguous metal line, wherein one end of each conductive plug contacts with the contiguous metal line, and the other end of at least one conductive plug is not connected to any conductor.

2. The test key of claim 1, wherein spin-on glass (SOG) is disposed beside the contiguous metal line.

3. The test key of claim 2, wherein a first dielectric layer is disposed between the contiguous metal line and the spin-on glass.

4. The test key of claim 2, wherein a second dielectric layer is disposed on the contiguous metal line and the spin-on glass, and the conductive plugs are disposed in the second dielectric layer.

5. The test key of claim 4, wherein a top portion of each conductive plug is wider than the other portions of the conductive plug, and a lower surface of the top portion of the conductive plug has a shape caused by selective isotropic etching to the second dielectric layer.

6. The test key of claim 1, further comprising at least two dummy patterns disposed beside the contiguous metal line and apart from the metal line by a distance.

7. The test key of claim 6, wherein the distance is equal to a distance between two adjacent metal layers in the interconnect structure, wherein the two adjacent metal layers are at the same level of the contiguous metal line.

8. The test key of claim 6, wherein a material of the at least two dummy patterns is the same as a material of the contiguous metal line.

9. The test key of claim 1, which is formed in a scribe line area of a wafer.

10. The test key of claim 1, wherein the conductive plugs comprise aluminum.

11. A test key for checking an interconnect structure, comprising:

a first, a second and a third contiguous metal lines that are arranged sequentially and are parallel to each other;

a plurality of conductive plugs on the first and the third contiguous metal lines, wherein a lower end of each conductive plug contacts with the first or third contiguous metal line; and

an upper metal layer disposed over the first to third contiguous metal lines and the conductive plugs, contacting with an upper end of each conductive plug.