Active Matrix Substrate, Display Apparatus, and Television Receiver

• US 20090065778A1
• Filed: 12/05/2006
• Published: 03/12/2009
• Est. Priority Date: 03/15/2006
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Takeuchi, Masanori, Tsubata, Toshihide
• Granted Patent: US 8,304,769 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity. The gate electrode of each transistor and a gate insulating film covering the conductor have a thin section with reduced thickness, in an on-conductor area overlapping the conductor. At least a part of the thin section overlaps the capacity electrode. In this way, the active matrix substrate which can reduce inconsistency in capacitance values of capacities (e.g. a storage capacitor, a capacity for controlling an electric potential of a pixel electrode, and a capacity which can function as both of them) provided in the substrate.

Claims

1. An active matrix substrate in which each pixel area has a transistor and a capacity electrode which is connected to the transistor and is able to function as an electrode of a capacity,

the active matrix substrate comprising:

a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity; and

an insulating film which covers the conductor,

the insulating film having a thin section with reduced thickness in an on-conductor area where the insulating film overlaps the conductor, at least a part of the thin section overlapping the capacity electrode.

2. The active matrix substrate as defined in claim 1,

wherein, the thin section is locally formed at a central part of the on-conductor area.

3. The active matrix substrate as defined in claim 1,

wherein, the entirety of the thin section overlaps the capacity electrode.

4. The active matrix substrate as defined in claim 1,

wherein, the insulating film is a gate insulating film covering a gate electrode of the transistor.

5. The active matrix substrate as defined in claim 4,

wherein, the capacity electrode is a pixel electrode connected with a drain electrode of the transistor.

6. The active matrix substrate as defined in claim 4,

wherein, the capacity electrode is a drain lead electrode which is an extension of a drain electrode of the transistor.

7. The active matrix substrate as defined in claim 4,

wherein, the conductor is a part of a storage capacity wire.

8. The active matrix substrate as defined in claim 4,

wherein, the conductor is a part of a scanning signal line of an immediately preceding or immediately subsequent stage in a scanning direction.

9. The active matrix substrate as defined in claim 5,

wherein, a pixel electrode is formed on the thin section with a first interlayer insulating film being interposed between the pixel electrode and the thin section, the first interlayer insulating film covering a channel part of the transistor.

10. The active matrix substrate as defined in claim 6,

wherein, the drain lead electrode is formed directly on the thin section.

11. The active matrix substrate as defined in claim 6,

wherein the drain lead electrode is formed on the thin section with a semiconductor layer being interposed therebetween.

12. The active matrix substrate as defined in claim 10,

wherein a contact hole is formed on the thin section, and the drain lead electrode contacts a pixel electrode in the contact hole.

13. The active matrix substrate as defined in claim 12,

wherein a first interlayer insulating film covering a channel part of the transistor and a second interlayer insulating film which is thicker than the thin section are provided on areas other than the contact hole between the pixel electrode and the gate insulating film.

14. The active matrix substrate as defined in claim 4,

wherein, the gate insulating film is constituted by plural gate insulating layers, and at least one of the gate insulating layers is arranged to be thin in the thin section.

15. The active matrix substrate as defined in claim 4,

wherein, the gate insulating film is constituted by plural gate insulating layers, at least one gate insulating layer being provided in the thin section, more gate insulating layers being provided in areas other than the thin section.

16. The active matrix substrate as defined in claim 15,

wherein, a gate insulating layer including an organic matter is provided.

17. The active matrix substrate as defined in claim 15,

wherein, at least one of the gate insulating layers is a flattening film.

18. The active matrix substrate as defined in claim 15,

wherein, the undermost gate insulating layer is a flattening film in the areas other than the thin section.

19. The active matrix substrate as defined in claim 15,

wherein, the undermost gate insulating layer is an SOG film made of a spin on glass (SOG) material in the areas other than the thin section, whereas no SOG film is provided in the thin section.

20. The active matrix substrate as defined in claim 18,

wherein, a part of the flattening film, which part contacts a surface of the substrate, is thicker than the conductor formed on the surface of the substrate.

21. The active matrix substrate as defined in claim 16,

wherein, the thickness of the gate insulating layer including the organic matter is 1.0 [μ

m] or more and 5.0 [μ

m] or less.

22. The active matrix substrate as defined in claim 15,

wherein, a first interlayer insulating film is provided on the gate insulating film so as to cover a channel part of the transistor, and the sum of the thickness of the gate insulating film and the thickness of the first interlayer insulating film is 1.65 [μ

m] or more and 5.65 [μ

m] or less in the areas other than the thin section.

23. The active matrix substrate as defined in claim 5,

wherein, the conductor is a circular storage capacity wire formed to overlap an edge of the pixel electrode.

24. The active matrix substrate as defined in claim 7,

wherein, a pixel electrode is provided as the capacity electrode and the pixel electrode has (i) an edge extending along a data signal line connected to a source electrode of the transistor and (ii) an edge facing that edge, and

the storage capacity wire is formed to overlap both of these edges.

25. The active matrix substrate as defined in claim 1,

wherein, a first pixel electrode is provided as the capacity electrode, and a second pixel electrode is provided so as to form a capacity with the conductor,

the capacity which is formed by the first pixel electrode and the conductor is connected in series with a capacity formed by the conductor and the second pixel electrode.

26. The active matrix substrate as defined in claim 25,

wherein, a drain electrode of the transistor is made of the same material as the conductor.

45. A display apparatus comprising the active matrix substrate defined in claim 1.

46. A television receiver comprising:

the display apparatus defined in claim 45; and

a tuner section receiving television broadcast.

27. An active matrix substrate in which each pixel area has:

first and second transistors;

a first capacity electrode which is connected to the first transistor and is able to function as an electrode of a first capacity; and

a second capacity electrode which is connected to the second transistor and is able to function as an electrode of a second capacity,

the active matrix substrate comprising;

a first conductor which is provided in a layer below the first capacity electrode and is able to function as the other electrode of the first capacity; and

a second conductor which is provided in a layer below the second capacity electrode and is able to function as the other electrode of the second capacity,

gate insulating films, covering gate electrodes of the transistors and the conductors, being provided with a first thin section with reduced thickness in a first on-conductor area overlapping the first conductor and with a second thin section with reduced thickness in a second on-conductor area overlapping the second conductor,

at least a part of the first thin section overlapping the first capacity electrode, at least a part of the second thin section overlapping the second capacity electrode.

28. The active matrix substrate as defined in claim 27,

wherein, the first thin section is locally formed at a central part of the first on-conductor area, and the second thin section is locally formed at a central part of the second on-conductor area.

29. The active matrix substrate as defined in claim 27,

wherein, the entirety of the first thin section overlaps the first capacity electrode, and the entirety of the second thin section overlaps the second capacity electrode.

30. The active matrix substrate as defined in claim 27, wherein, the first capacity electrode is a first pixel electrode connected to a drain electrode of the first transistor, the second capacity electrode is a second pixel electrode connected to a drain electrode of the second transistor, and the first and second pixel electrodes are formed in each pixel area.

31. The active matrix substrate as defined in claim 27,

wherein, the first capacity electrode is a first drain lead electrode which is an extension of a drain electrode of the first transistor, and the second capacity electrode is a second drain lead electrode which is an extension of a drain electrode of the second transistor.

32. The active matrix substrate as defined in claim 30,

wherein, the first and second constructors are parts of first and second storage capacity wires, respectively, and are able to individually control electric potentials of the first and second storage capacity wires, and electric potentials of the first and second pixel electrodes are individually controlled by this potential control.

33. The active matrix substrate as defined in claim 31,

wherein, each pixel area is provided with a first pixel electrode connected to the drain electrode of the first transistor and a second pixel electrode connected to the drain electrode of the second transistor, and

the first and second conductors are parts of first and second storage capacity wires, respectively, and are able to individually control electric potentials of the first and second storage capacity wires, and electric potentials of the first and second pixel electrodes are individually controlled by this potential control.

34. The active matrix substrate as defined in claim 32,

wherein, the electric potential of the first storage capacity wire is controlled in such a way that the electric potential increases after each of the transistors is turned off and an increased state continues until each of the transistors is turned off in a next frame, and the electric potential of the second storage capacity wire is controlled in such a way that the electric potential decreases after each of the transistors is turned off and a decreased state continues until each of the transistors is turned off in a next frame, or

the electric potential of the first storage capacity wire is controlled in such a way that the electric potential decreases after each of the transistors is turned off and a decreased state continues until each of the transistors is turned off in a next frame, and the electric potential of the second storage capacity wire is controlled in such a way that the electric potential increases after each of the transistors is turned off and an increased state continues until each of the transistors is turned off in a next frame.

35. The active matrix substrate as defined in claim 34,

wherein, an increase in the electric potential of the first storage capacity wire occurs one horizontal period before or after a decrease in the electric potential of the second storage capacity wire, or a decrease in the electric potential of the first storage capacity wire occurs one horizontal period before or after an increase in the electric potential of the second storage capacity wire.

36. The active matrix substrate as defined in claim 27,

wherein, the first and second capacity electrodes are respectively formed on the first and second thin sections, directly or with either a semiconductor layer or a first interlayer insulating film covering a channel part of each of the transistors being interposed therebetween.

37. The active matrix substrate as defined in claim 27,

wherein, the gate insulating film is constituted by plural gate insulating layers,

at least one gate insulating layer being provided in the first and second thin sections, more gate insulating layers being provided in areas other than the first and second thin sections.

38. The active matrix substrate as defined in claim 37,

wherein, a gate insulating layer including an organic matter is provided.

39. The active matrix substrate as defined in claim 37,

wherein, the undermost gate insulating layer is an SOG film made of a spin on glass (SOG) material in the areas other than the first and second thin sections, whereas no SOG film is provided in the first and second thin sections.

40. The active matrix substrate as defined in claim 27,

wherein, the gate insulating layer has another thin section with reduced thickness in an area overlapping the semiconductor layer of the first and second transistors.

41. The active matrix substrate as defined in claim 27,

wherein, areas around edges of the thin section of the gate insulating film are arranged to have a forward tapered shape.

47. A display apparatus comprising the active matrix substrate defined in claim 27.

42. An active matrix substrate comprising a transistor, a conductor, an insulating film covering the conductor, and a capacity electrode provided in a layer above the insulating film to form a capacity with the conductor, the capacity electrode being connected to the transistor,

the insulating film having reduced thickness at a part of an area where the insulating film overlaps the capacity electrode and the conductor.

43. The active matrix substrate as defined in claim 42,

wherein, the insulating film includes an insulating layer made of an SOG (spin on glass) material in areas other than the part with reduced thickness, whereas there is provided no insulating layer made of the SOG material in the part with reduced thickness.

44. The active matrix substrate as defined in claim 42,

wherein, the insulating film is a gate insulating film covering a gate electrode of the transistor,

the conductor is a storage capacity wire, and

the capacity electrode is either a pixel electrode connected to a drain electrode of the transistor or a drain lead electrode which is an extension of the drain electrode of the transistor.

48. A display apparatus comprising the active matrix substrate defined in claim 42.