FIN FIELD EFFECT TRANSISTOR

• US 20090065853A1
• Filed: 09/07/2007
• Published: 03/12/2009
• Est. Priority Date: 09/07/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hanafi, Hussein I.
• Granted Patent: US 7,674,669 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: Y10S 438/933 Germanium or silicon or Ge-Si on III-V

Abstract

Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si_1-XGe_X) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.

Claims

1. A method for forming a FinFET, comprising:

forming a relaxed silicon germanium (Si_1-XGe_X) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;

forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation; and

forming a gate opposing the body region and separated therefrom by a gate dielectric.

4. The method of claim 1, wherein the method includes epitaxially growing a silicon (Si) layer on a sidewall on the body region to provide biaxial tensile strain to the body region in forming an NMOS FinFET.

5. The method of claim 4, wherein the method includes epitaxially growing the Si layer on the sidewall on the body region to a thickness of approximately 6 nm.

6. The method of claim 1, wherein the method includes forming a channel between the source and the drain having a width less than 35 nm and a length less than 25 nanometers.

7. The method of claim 1, wherein forming the source and the drain with halo ion implantation includes:

forming a p-type source and drain having a Boron (B) dopant at a concentration of 2×

10²⁰ atoms/cm³; and

forming a halo ion implant underneath the p-type source drain having a concentration of 2×

10¹⁸ atoms/cm³.

8. The method of claim 1, wherein forming the source and the drain with halo ion implantation includes:

forming an n-type source and drain having an Arsenic (As) dopant at a concentration of 2×

10²⁰ atoms/cm³; and

forming a halo ion implant underneath the n-type source and drain having a concentration of 2×

10¹⁸ atoms/cm³.

2. The method of claim l, wherein the method includes epitaxially growing a germanium (Ge) layer on a sidewall on the body region to provide biaxial compressive strain to the body region in forming a PMOS FinFET.

3. The method of claim 2, wherein the method includes epitaxially growing the Ge layer on the sidewall on the body region to a thickness of approximately 12 nm.

9. A method for forming a FinFET, comprising:

forming a relaxed silicon germanium (Si_1-XGe_X) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;

forming a substitute gate over the body region;

forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation;

annealing the source and the drain before removing the substitute gate; and

forming a gate separated from the body region by a gate dielectric.

10. The method of claim 9, wherein the method includes forming a source extension and a drain extension while the substitute gate is present on the device.

11. The method of claim 9, wherein the method includes epitaxially growing a germanium (Ge) sidewall on the body region to provide biaxial compressive strain on the body region in forming a PMOS FinFET.

12. The method of claim 9, wherein the method includes epitaxially growing a silicon (Si) sidewall on the body region to provide biaxial tensile strain on the body region in forming an NMOS FinFET.

13. The method of claim 9, wherein forming the relaxed silicon germanium (Si_1-XGe_X) body region includes forming a forming a relaxed silicon germanium (Si_1-XGe_X) where X is in a range of 0.5 to 0.6.

14. The method of claim 9, wherein annealing the source and the drain before removing the substitute gate includes annealing at a temperature in a range of 850 degrees Celsius to 1050 degrees Celsius for a period of at least 5 seconds to activate the source and the drain.

15. The method of claim 14, wherein forming the gate includes forming a metal gate separated from the body region by a dielectric material having a dielectric constant (K) greater than 12.

16. A FinFET, comprising:

a FinFET having a fully depleted, relaxed silicon germanium (Si_1-XGe_X) body region, wherein the body region has a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm;

a channel formed in a sidewall of the body region, wherein the sidewall is epitaxially strained.

17. The FinFET of claim 16, wherein the channel has a width of less than 35 nm and a length of less than 25 nanometers.

18. The FinFET of claim 16, wherein the cell is a NMOS cell and wherein the sidewall is under biaxial tensile strain from a layer of Silicon (Si) formed on the relaxed silicon germanium (Si_1-XGe_X) body region sidewall.

19. The FinFET of claim 18, wherein the layer of Silicon (Si) includes a thickness of approximately 6 nm.

20. The FinFET of claim 16, wherein the cell is a PMOS cell and wherein the sidewall is under biaxial compressive strain from a layer of Germanium (Ge) formed on the relaxed silicon germanium (Si_1-XGe_X) body region sidewall.

21. The FinFET of claim 20, wherein the layer of Germanium (Ge) includes a thickness of approximately 12 nm.

22. The FinFET of claim 16, wherein a source and a drain with halo ion implantation includes:

a p-type source and drain having a Boron (B) dopant at a concentration of 2×

10²⁰ atoms/cm³; and

a halo ion implant underneath the p-type source and drain having a concentration of 2×

10¹⁸ atoms/cm³.

23. The FinFET of claim 16, wherein a source and a drain with halo ion implantation includes:

an n-type source and drain having an Arsenic (As) dopant at a concentration of 2×

10²⁰ atoms/cm³; and

a halo ion implant underneath the n-type source and drain having a concentration of 2×

10¹⁸ atoms/cm².

24. The FinFET of claim 16, wherein the cell includes a metal gate opposing the channel and separated therefrom by a dielectric material having a dielectric constant (K) greater than 12.

25. The FinFET of claim 16, wherein the cell includes the relaxed silicon germanium (Si_1-XGe_X) with X in a range of 0.5 to 0.6.