Reprogrammable three dimensional field programmable gate arrays

• US 20090066365A1
• Filed: 09/12/2008
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Solomon Research LLC
• Original Assignee: Solomon Research LLC
• Inventors: Solomon, Neal
• Granted Patent: US 7,692,448 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

3D FPGAs are elucidated with (a) interlayer information sharing, (b) intermittent and variable timing of layer configuration and (c) multilayer multi-functionality. 3D FPGAs are applied to reprogrammable SoCs.

Claims

1. A system for organizing reprogrammable three dimensional (3D) field programmable gate arrays (FPGAs), comprising:

a set of arrays of logic and memory components on two or more layers of a hybrid multilayer logic device;

a set of SRAM tiles on the outer edge of each layer;

a set of logic block arrays on tiles in the interior of each layer arranged in symmetrical rows connected by interconnects and TSVs;

a set of switch matrices on tiles in the interior of each layer to connect the logic block arrays and the memory components with interconnects and TSVs;

a set of look up tables (LUTs) on memory tiles for access to arithmetic data;

movable interconnects within the logic block arrays that change position when activated by at least one switch matrix from one ASIC position to another ASIC position; and

a set of TSVs that connect the tiles of one layer to the tiles of an adjacent layer.

2. A system of claim 1, wherein:

The interconnects are positioned vertically between adjacent layers of the multilayer FPGA;

The vertical interconnects move position when activated by at least one switch matrix; and

The vertical interconnects activate the logic block array of one layer of the multilayer FPGA from the switch matrix of an adjacent layer.

3. A system of claim 1, wherein:

A flexible joint activates the vertical interconnects to move position when activated by a switch matrix on an adjacent layer of a multilayer FPGA;

The flexible joint moves at a 90 degree arc when positioned in a corner position;

The flexible joint moves at a 180 degree arc when positioned in a side position on a tile; and

The flexible joint moves at a 270 degree arc when positioned in a center position on a tile.

4. A system of claim 1, wherein:

Two flexible joints are activated on tiles of adjacent layers to activate the vertical interconnects to move position to meet in the middle when activated by two synchronized switch matrices of a 3D FPGA.

5. A system for organizing one or more layers of reprogrammable three dimensional (3D) field programmable gate arrays (FPGAs) in a multi-layer integrated circuit, comprising:

a set of arrays of logic and memory components on one or more layers of a hybrid multi-layer integrated circuit, each with a set of SRAM tiles, logic block array tiles and switch matrix tiles; and

wherein the logic components of an FPGA layer store data and instructions in and access data and instructions from memory components on other layers of the multi-layer integrated circuit.

6. A system of claim 5, wherein:

At least one FGPA layer and at least one microprocessor layer are synchronized to work together to perform separate computational tasks in the multi-layer hybrid integrated circuit;

The FPGA layer activates specific application devices; and

The microprocessor layer activates specific application devices.

7. A system of claim 5, wherein:

Two or more FPGA layers in the multi-layer hybrid integrated circuit store data and instructions in and access data and instructions from SRAM tiles of adjacent layers; and

The storing of and access to data and instructions in adjacent FPGA layers are performed by multiple parallel pipelines.

8. A system of claim 5, wherein:

One or more FPGA layers on a multi-layer hybrid integrated circuit store data and instructions in and access data and instructions from DRAM layers of other multi-layer memory modules.

9. A system for organizing one or more layers of reprogrammable three dimensional (3D) field programmable gate arrays (FPGAs) in a multi-layer integrated circuit, comprising:

a set of arrays of logic and memory components on one or more layers of a hybrid multi-layer integrated circuit, each with a set of SRAM tiles, logic block array tiles and switch matrix tiles;

wherein when the environment changes, a sensor is activated in the device application for each FPGA layer and the FPGA layer reconfigures the interconnects in the logic block arrays to a different ASIC layout structure; and

wherein the multi-layer FPGA uses D-EDA modeling to design the customized placement and routing configuration of each change of phase state of the FPGA as it reprograms.

10. The system of claim 9, wherein:

One layer in the multi-layer hybrid IC models at least one FPGA layer for reconfiguration;

11. The system of claim 9, wherein:

At least one FPGA layer is reconfigured to solve evolving MOOPs as the environment changes;

As at least one FPGA layer restructures its logic block array to at least two configurations in a sequence, the data of the restructuration pattern are stored in a database;

When the multi-layer FPGA seeks to solve MOOPs in an evolving environment, it accesses the database to assess the new MOOPs by analyzing the factors of the past solutions; and

At least one layer of the multi-layer FPGA solves MOOPs and continuously restructures its logic block arrays while reprogramming all the layers in the multi-layer FPGA.