Reprogrammable three dimensional intelligent system on a chip

• US 20090066366A1
• Filed: 09/12/2008
• Published: 03/12/2009
• Est. Priority Date: 09/12/2007
• Status: Active Grant

• Current Assignee: Solomon Research LLC
• Original Assignee: Solomon Research LLC
• Inventors: Solomon, Neal
• Granted Patent: US 7,772,880 B2
• Time in Patent Office: Days
• US Class Current: 326/41
• CPC Class Codes: G06F 15/17387 Three dimensional, e.g. hypercubes
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A high performance 3D semiconductor is described with cubic dimensional multi-node reprogrammable components for multi-functionality and intelligent behaviors. The system is modeled with dynamic EDA techniques. Applications of the intelligent SoC are specified, particularly embedded, multifunctional, DSP and high-performance computing applications.

Claims

1. A system for organizing multilayer integrated circuit (IC) nodes in a three dimensional (3D) system on a chip (SoC), comprising:

35 3D hybrid IC nodes organized in a network configuration;

wherein the nodes are organized to process data and instructions;

wherein the IC nodes are hybrid semiconductors consisting of microprocessors, complex programmable logic devices, ASICs and memory components;

wherein the IC nodes are linked to each other;

wherein 34 of the IC nodes are organized in neighborhood clusters;

wherein 1 of the IC nodes is a central controller node;

wherein the configuration of each neighborhood cluster varies with specific tasks;

wherein the 3D SoC receives signals from exogenous sources; and

wherein the 3D SoC controls device applications.

2. A system of claim 1, wherein:

The configuration of the set of nodes in each neighborhood cluster changes its composition of nodes when activated by specific applications;

The minimum number of nodes in a neighborhood are two, including a corner node and an inside node;

The maximum number of nodes in a neighborhood is eight.

3. A system of claim 1, wherein:

One neighborhood cluster sends data and instructions to and receives data and instructions from other neighborhood clusters.

4. A system of claim 1, wherein:

Specific neighborhood clusters are inactive when applications are dormant.

5. A system of claim 1, wherein:

The SoC solves multi-objective optimization problems (MOOPs) by forwarding MOOPs to the several neighborhood clusters for simultaneous analysis until the problems are solved.

6. A system of claim 1, wherein:

The 3D SoC is used for DSP, embedded and multifunctional applications.

7. A system for applying dynamic EDA tools for placement and routing of interconnect and TSV networks in multilayer integrated circuit (IC) nodes in a three dimensional (3D) system on a chip (SoC), comprising:

A modeling component to organize the scenarios of network architecture options;

An analytical component to select the placement and routing architecture within optimization constraints;

The testing and refinement of a final 3D IC architecture map; and

Implementation of the 3D architecture into the 3D SoC.

8. A system of claim 7, wherein:

The D-EDA process, the model, the analysis and the testing of the 3D IC architecture map is performed using intelligent mobile software agents (IMSAs).

9. A system of claim 7, wherein:

The 3D SoC is reconfigurable to solve evolving MOOPs.

10. A system of claim 7, wherein:

A neighborhood cluster performs the D-EDA process to reconfigure the SoC.

11. A system of claim 7, wherein:

The reconfiguration of the 3D nodes in the SoC occurs in response to an evolving environment; and

The applications controlled by the SoC are interactive in real time to the environment.