DIGITAL CALIBRATION CIRCUITS, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION
First Claim
1. A calibration circuit comprising:
- a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals;
a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value; and
a binary searcher coupled to receive the first and second control signals, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count.
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Accused Products
Abstract
A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.
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Citations
88 Claims
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1. A calibration circuit comprising:
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a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value; and a binary searcher coupled to receive the first and second control signals, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (65, 66, 67, 68, 69)
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2-64. -64. (canceled)
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70. A memory device, comprising:
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an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and a calibration circuit for a driver comprising; a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value; and a binary searcher coupled to receive the first and second control signals, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (71, 72, 73)
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74. A computer system, comprising:
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a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device coupled to the processor, the memory device comprising; an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the control bus; an array of memory cells coupled to the address decoder, control circuit, and read/write circuit; an output driver circuit for outputting data read from the array of memory cells; and a calibration circuit for a driver comprising; a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals; a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value; and a binary searcher coupled to receive the first and second control signals, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count. - View Dependent Claims (75, 76, 77, 78)
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79. A method for calibrating a driver, the method comprising:
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comparing the output impedance of a driver to a target output impedance to determine if the output impedance is within a range of the target output impedance; adjusting the output impedance using a first adjustment type if the output impedance is within the predetermined range of the target impedance; and adjusting the output impedance of the driver using a second adjustment type if the output impedance is outside the predetermined range of the target impedance. - View Dependent Claims (80, 81, 82, 83)
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84. A method for calibrating a driver, the method comprising:
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comparing the output impedance of the driver to a target output impedance to determine if the output impedance is within a first range of the target output impedance or a second range of the target output impedance; adjusting the output impedance of the driver in binary steps if the output impedance is within a first range of the target output impedance; adjusting the output impedance of the driver in binary substeps if the output impedance is within a second range of the target output impedance; repeating at least one comparison and adjustment of the output impedance of the driver to a target output impedance; and outputting a final impedance of the driver based on the at least one comparison. - View Dependent Claims (85, 86, 87, 88)
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Specification